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US 11,636,174 B2Granted
Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs
AssigneeIntel Corporation
InventorsSubramaniam Maiyuran, Jorge Parra, Supratim Pal, Ashutosh Garg, Shubra Marwaha, Chandra Gurram, Darin Starkey, Durgesh Borkar, Varghese George
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Abstract
Described herein is an accelerator device including a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a systolic array with feedback inputs.
Claims20
An accelerator device comprising:
- a host interface;
- a fabric interconnect coupled with the host interface;
- and
- one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a modular systolic processing array with feedback inputs, the modular systolic processing array including one or more processing array modules including a first pipeline path configurable to execute a first dot product instruction having a first set of inputs and a second pipeline path configurable to execute a second dot product instruction having a second set of inputs.
1 more element
A graphics processor comprising:
- a host interface;
- a fabric interconnect coupled with the host interface;
- and
- one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a modular systolic processing array with feedback inputs, the modular systolic processing array including one or more processing array modules including a first pipeline path configurable to execute a first dot product instruction having a first set of inputs and a second pipeline path configurable to execute a second dot product instruction having a second set of inputs.
1 more element
A data processing system comprising:
- a host interface;
- a memory device coupled with the host interface;
- a fabric interconnect coupled with the host interface and the memory device;
- and
- one or more hardware tiles coupled with the fabric interconnect and the memory device, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a modular systolic processing array with feedback inputs, the modular systolic processing array including one or more processing array modules including a first pipeline path configurable to execute a first dot product instruction having a first set of inputs and a second pipeline path configurable to execute a second dot product instruction having a second set of inputs.
2 more elements
Dependencies are inferred from the claim text.