Method and apparatus for performing access management of memory device in predetermined communications architecture with aid of flexible delay time control

A memory device, comprising:

• a non-volatile (NV) memory, arranged to store information, wherein the NV memory comprises at least one NV memory element;
• and
• a controller, coupled to the NV memory, arranged to control operations of the memory device, wherein the controller comprises:
• a processing circuit, arranged to control the controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the controller;
• and
• a transmission interface circuit, arranged to perform communications with the host device, wherein the transmission interface circuit comprises:
• a physical layer (PHY) circuit, arranged to perform transmitting and receiving operations for the transmission interface circuit;
• and
• at least one upper layer controller, arranged to control operations of the PHY circuit according to a predetermined specification;
• wherein:
• the controller utilizes the at least one upper layer controller to dynamically set a delay parameter regarding transmission from the memory device to the host device, for preventing sleeping in at least one delay time corresponding to the delay parameter, wherein the delay parameter is dynamically set as one of multiple predetermined values, rather than being set as a single fixed value;
• the controller utilizes the PHY circuit to transmit first data from the memory device to the host device, wherein a first delay time measured with respect to the first data among the at least one delay time starts from a first time point at which transmitting the first data from the memory device to the host device is completed;
• and
• the controller utilizes the PHY circuit to start transmitting second data from the memory device to the host device in the first delay time without restarting from sleeping.

A controller of a memory device, the memory device comprising the controller and a non-volatile (NV) memory, the NV memory comprising at least one NV memory element, the controller comprising:

• a processing circuit, arranged to control the controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the controller;
• and
• a transmission interface circuit, arranged to perform communications with the host device, wherein the transmission interface circuit comprises:
• a physical layer (PHY) circuit, arranged to perform transmitting and receiving operations for the transmission interface circuit;
• and
• at least one upper layer controller arranged to control operations of the PHY circuit according to a predetermined specification;
• wherein:
• the controller utilizes the at least one upper layer controller to dynamically set a delay parameter regarding transmission from the memory device to the host device, for preventing sleeping in at least one delay time corresponding to the delay parameter, wherein the delay parameter is dynamically set as one of multiple predetermined values, rather than being set as a single fixed value;
• the controller utilizes the PHY circuit to transmit first data from the memory device to the host device, wherein a first delay time measured with respect to the first data among the at least one delay time starts from a first time point at which transmitting the first data from the memory device to the host device is completed;
• and
• the controller utilizes the PHY circuit to start transmitting second data from the memory device to the host device in the first delay time without restarting from sleeping.