Memory controller power states

A method, comprising:

• at a local power state controller of a first memory controller, receiving a first power state command;
• in response to receiving the first power state command:
• causing configuration and state data from control registers in the memory controller to be stored in an on-chip RAM memory;
• causing the first memory controller to enter a powered-down state in which a first voltage domain is powered down;
• and
• providing a signal indicating the first memory controller is ready for isolation cells in the first memory controller to isolate a physical layer interface (PHY) from the first voltage domain of the first memory controller.

A data processing system, comprising:

• a data fabric;
• a first memory channel coupled to an associated DRAM memory;
• and
• a first memory controller coupled to the data fabric and the first memory channel for fulfilling memory access requests received over the data fabric, the first memory controller comprising:
• a command queue for receiving memory access requests for a first memory channel, and an arbiter for selecting entries from the command queue for transmission over the first memory channel, the command queue and arbiter operating in a first voltage domain;
• a DRAM physical layer interface (PHY) operating in a second voltage domain for coupling the first memory controller to a DRAM memory associated with the first memory channel;
• a local power state controller which, in response to a first power state command, provides configuration and state data for storage in an on-chip RAM memory;
• and
• isolation cells operable to isolate the DRAM PHY from the first voltage domain, wherein the local power state controller, in response to the first power state command, provides a signal indicating readiness for the isolation cells to isolate the DRAM PHY from the first voltage domain.