Memory protection with hidden inline metadata
AssigneeIntel Corporation
InventorsDavid M. Durham, Ron Gabor
Life of this patent
Estimating the term…
Abstract
Embodiments are directed to memory protection with hidden inline metadata. An embodiment of an apparatus includes processor cores; a computer memory for the storage of data; and cache memory communicatively coupled with one or more of the processor cores, wherein one or more processor cores of the plurality of processor cores are to implant hidden inline metadata in one or more cachelines for the cache memory, the hidden inline metadata being hidden at a linear address level.
Claims20
An apparatus comprising:
- a plurality of processor cores;
- and
- memory for storage of data;
- wherein one or more processor cores of the plurality of processor cores are to implant hidden inline metadata in one or more portions of the memory, hidden inline metadata for a first portion of the memory including one or more memory tags, the hidden inline metadata being hidden for linear address operations;
- and
- wherein the one or more processor cores are to compare the one or more memory tags in the hidden inline metadata for the first portion of the memory with a memory pointer tag value in a linear address to determine whether a memory access is authorized.
One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
- implanting hidden inline metadata in one or more portions of a memory of a computing system, hidden inline metadata for a first portion of the memory including one or more memory tags, the hidden inline metadata being hidden for linear address operations;
- and
- comparing the one or more memory tags in the hidden inline metadata for the first portion of the memory with a memory pointer tag value in a linear address to determine whether a memory access is authorized.
A method comprising:
- implanting hidden inline metadata in one or more portions of a memory of a computing system, hidden inline metadata for a first portion of the memory including one or more memory tags, the hidden inline metadata being hidden for linear address operations;
- and
- comparing the one or more memory tags in the hidden inline metadata for the first portion of the memory with a memory pointer tag value in a linear address to determine whether a memory access is authorized.
Dependencies are inferred from the claim text.