Latency free data encryption and decryption between processor and memory

A hardware circuit for encrypting and/or decrypting data transmitted between a processor and a memory, the circuit comprising:

• a first interface communicatively coupled to the processor via a first bus, the processor having a first clock;
• a second interface communicatively coupled to the memory via a second bus, the memory associated with a data transmission speed and the memory having a second clock, wherein the memory is a double data rate 4 (DDR4) SDRAM with a high bandwidth DDR4 interface;
• and
• hardware logic capable of executing an encryption operation on data transmitted between the processor and memory at a given clock time at a data transmission speed of DDR4 interface, without adding latency to the data transmission speed of the memory, the hardware logic configured to:
• encrypt data received at the first interface from the processor, and transmit the encrypted data to the memory via the second interface, and decrypt data received at the second interface from the memory, and transmit the decrypted data to the processor via the first interface synchronize encryption of the data received at the first interface relative to the second clock.

A computer-implemented method of encrypting and/or decrypting data, the method comprising:

• receiving data at an encryption circuit situated between a processor and memory, wherein the memory is a double data rate 4 (DDR4) SDRAM with a high bandwidth DDR4 interface,
• the memory associated with a data transmission speed, and the encryption circuit operatively coupled to the processor via a first bus and operatively coupled to the memory via a second bus;
• and
• executing an encryption operation on the data without adding latency to the data transmission speed of the memory, wherein the encryption circuit is configured to execute the encryption operation on the data within a given clock time, such that the encryption circuit transmits the data at data transmission speed of the DDR4 interface, and further wherein:
• if the data is received from the processor, encrypting and transmitting the data to the memory, wherein encrypting the data is synchronized relative to a clock of the memory;
• and
• if the data is received from the memory, decrypting and transmitting the data to the processor.