Translating virtual addresses in a virtual memory based system

A method of translating a virtual address to a second address in a memory module having a memory controller and a plurality of memory devices for storing data, wherein the memory module is remote from a processor, a translation buffer (TB) for storing a plurality of Page Table Entries (PTE), and a Page Walk Cache for storing a plurality of page directory entries, the method comprising:

• receiving by the memory controller from the processor a page directory base combined with a first level memory offset and at least a second level memory offset;
• reading by the memory controller a first level page directory entry using the page directory base combined with the first level memory offset;
• combining the second level memory offset and the first level page directory entry by the memory controller;
• reading by the memory controller a second level page directory entry using the first level page directory entry and the second level memory offset;
• sending, by the memory controller to the processor for storing in a PWC on the processor, at least one of a group consisting of the first level page directory entry, the second level page directory entry, and combinations thereof;
• and
• sending a page table entry (PTE) by the memory controller to the processor for storing in a TB on the processor.

A computer program product for translating a virtual address to a second address in a memory module having a memory controller and one or more memory devices having a plurality of locations for storing data, each location having a physical address, wherein the memory module is remote from a processor, a translation buffer (TB) for storing a plurality of Page Table Entries (PTE), and a Page Walk Cache for storing a plurality of page directory entries, the computer program product comprising:

• one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, the program instructions comprising:
• program instructions to receive by the memory controller from the processor a page directory base and a plurality of memory offsets, wherein the plurality of memory offsets includes at least a first level memory offset and a second level memory offset;
• program instructions to read by the memory controller a first level page directory entry using the page directory base and the first level memory offset;
• program instructions to combine the second level memory offset and the first level page directory entry by and in the memory controller;
• program instructions to read by the memory controller a second level page directory entry using the first level page directory entry and the second level memory offset;
• program instructions to send, by the memory controller to the processor for storing in a PWC on the processor, at least one of a group consisting of the first level page directory entry, the second level page directory entry, and combinations thereof;
• and
• program instructions to send a page table entry (PTE) by the memory controller to the processor for storing in a TB on the processor.