Write-back cache policy to limit data transfer time to a memory device
AssigneeMicron Technology, Inc.
InventorTony M. Brewer
Life of this patent
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Abstract
Systems, apparatuses, and methods related to a write-back cache policy to limit data transfer time to a memory device are described. A controller can orchestrate performance of operations to write data to a cache according to a write-back policy and write addresses associated with the data to a buffer. The controller can further orchestrate performance of operations to limit an amount of data stored by the buffer and/or a quantity of addresses stored in the buffer. In response to a power failure, the controller can cause the data stored in the cache to be flushed to a persistent memory device in communication with the cache.
Claims20
A method, comprising:
- writing data associated with each of a plurality of write requests to a cache of a memory system;
- writing addresses corresponding to the data associated with the plurality of write requests to buffer circuitry coupled to the cache;
- monitoring a quantity of addresses written to the buffer circuitry, or an amount of data written to the cache, or both, to determine whether the cache contains greater than a threshold quantity of data associated with the plurality of write requests;
- and
- writing the data from the cache to a memory device of the memory system responsive to a determination that the memory system has experienced a power event.
An apparatus, comprising:
- buffer circuitry;
- a cache coupled to the buffer circuitry;
- a memory device coupled to the cache;
- and
- a controller coupled to the buffer circuitry, the cache, and the memory device, wherein the controller is configured to:
- write data associated with a plurality of memory requests to the cache;
- write addresses associated with the data associated with the plurality of memory requests to the buffer circuitry;
- determine whether the buffer circuitry contains greater than a threshold quantity of addresses associated with the plurality of memory requests, or the cache contains greater than a threshold quantity of data associated with the plurality of memory requests, or both;
- and
- write the data from the cache to the memory device responsive to a determination that the memory device has experienced a power event.
A system, comprising:
- buffer circuitry;
- a cache coupled to the buffer circuitry;
- a memory device coupled to the cache;
- and
- a controller coupled to the buffer circuitry, the cache, and the memory device, wherein the controller is configured to:
- write data associated with a plurality of memory requests to the cache;
- write addresses corresponding to the data associated with the plurality of memory requests to the buffer circuitry;
- determine whether the buffer circuitry contains greater than a threshold quantity of addresses associated with the plurality of memory requests or whether the cache contains greater than a threshold quantity of data associated with the plurality of memory requests, or both;
- cause at least a portion of the data written to the cache to be prioritized for writing to the memory device responsive to a determination that the quantity of addresses written to the buffer circuitry contains greater than the threshold quantity of addresses associated with the plurality of memory operations or responsive to a determination that the cache contains greater than a threshold quantity of data associated with the plurality of memory requests, or both;
- and
- write the data from the cache to the memory device responsive to receipt of signaling indicative of a power event experienced by the system.
Dependencies are inferred from the claim text.