Pausing execution of a first machine code instruction with injection of a second machine code instruction in a processor

A method of executing instructions in a processor, the method comprising:

• fetching a first instruction from a memory of the processor, the first instruction requiring multiple cycles for execution;
• commencing execution of the first instruction in an execution pipeline of the processor, the execution pipeline having multiple execution stages configured to execute the first instruction to implement functional behaviour of the first instruction;
• receiving in the execution pipeline a second instruction during execution of the first instruction in one of the multiple execution stages of the execution pipeline;
• pausing execution of the first instruction in the execution pipeline;
• executing the second instruction to termination;
• and
• automatically recommencing execution of the first instruction on detection of termination of the second instruction.

A processing system comprising a first processor and a second processor and an interconnect for communicating between the first processor and the second processor, wherein:

• the first processor comprises an execution unit for executing machine code instructions, including a first machine code instruction requiring multiple cycles for execution;
• the interconnect is operable to conduct communications between the first processor and the second processor according to a bulk synchronous parallel scheme whereby each of the first processor and the second processor performs a local compute phase followed by an inter-processor exchange phase with the exchange phase being held back until both the first processor and the second processor have completed the compute phase, wherein the first machine code instruction comprises a synchronisation instruction for execution by the first processor upon completion of its compute phase;
• and
• wherein the execution unit is configured:
• to pause execution of the synchronisation instruction to execute an additional instruction which has been injected into the execution unit;
• to detect termination of execution of the additional instruction;
• and
• to automatically recommence execution of the synchronisation instruction on detection of termination of the additional instruction.

A method performed by a processor having an execution pipeline with multiple execution stages, the method comprising:

• accessing an instruction memory of the processor to fetch a first machine code instruction for execution in the execution pipeline, the first machine code instruction requiring multiple cycles of pipeline operation for execution;
• injecting a second machine code instruction into the execution pipeline of the processor during execution of the first machine code instruction in one of the multiple execution stages of the execution pipeline;
• pausing execution of the first machine code instruction at the one of the multiple execution stages in the execution pipeline while executing the second machine code instruction to termination in the execution pipeline;
• and
• recommencing execution of the first machine code instruction by the execution pipeline on detection of termination of the second machine code instruction.