Apparatuses and methods for speculative execution side channel mitigation

A method comprising:

• transitioning a first logical core of at least one logical core of a processor core of a processor to a more privileged predictor mode from a less privileged predictor mode;
• setting an indirect branch restricted speculation bit for the first logical core in a model specific register of the processor to a value after the transitioning of the first logical core to the more privileged predictor mode to prevent a branch predictor of the processor from predicting, based on software executed in the less privileged predictor mode by any of the at least one logical core, a target instruction of an indirect branch instruction for the first logical core, and allow the branch predictor to predict a second target instruction of a second indirect branch instruction based on software executed in the more privileged predictor mode when the indirect branch restricted speculation bit is set to the value after the transitioning of the first logical core to the more privileged predictor mode;
• and
• performing at least one data fetch operation with an instruction execution pipeline of the processor core for the target instruction before execution of the target instruction by the first logical core.

A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:

• transitioning a first logical core of at least one logical core of a processor core of a processor to a more privileged predictor mode from a less privileged predictor mode;
• setting an indirect branch restricted speculation bit for the first logical core in a model specific register of the processor to a value after the transitioning of the first logical core to the more privileged predictor mode to prevent, a branch predictor of the processor from predicting, based on software executed in the less privileged predictor mode by any of the at least one logical core, a target instruction of an indirect branch instruction for the first logical core, and allow the branch predictor to predict a second target instruction of a second indirect branch instruction based on software executed in the more privileged predictor mode when the indirect branch restricted speculation bit is set to the value after the transitioning of the first logical core to the more privileged predictor mode;
• and
• performing at least one data fetch operation with an instruction execution pipeline of the processor core for the target instruction before execution of the target instruction by the first logical core.