Managing memory device with processor-in-memory circuit to perform memory or processing operation

A method of operating a memory device comprising a memory including a plurality of memory banks, the method comprising:

• storing a plurality of instructions received from a host that correspond to a processing operation in an instruction memory of the memory device while the memory device is in an instruction loading mode;
• decoding an address received from the host to determine whether the address belongs to one of a first range and a second range different from the first range;
• decoding a command received from the host to determine whether to process an operand received from the host or an operand stored in one of the memory banks when the address belongs to the second range;
• the memory device entering a memory operation mode when it is determined that the address belongs to the first range and entering an operation processing mode when it is determined that the address belongs to the second range, after storage of the plurality of instructions in the instruction memory completes during the instruction loading mode;
• performing a memory operation corresponding to the received command and the received address when the memory device enters the memory operation mode;
• and
• reading a given instruction among the plurality of instructions and a processor in memory (PIM) circuit provided in the memory device performing a processing operation corresponding to the read given instruction on the operand when the memory device enters the operation processing mode,
• wherein it is determined that the address belongs to one of the first range and the second range from a bit value of at least one bit of the address, and
• wherein a part of the received address different from the at least one bit indicates a position of the operand in the one memory bank through a row address and a column address included in information of the part, when it is determined that the operand stored in the one memory bank is to be processed, and
• wherein, in the instruction loading mode, the plurality of instructions are stored in the instruction memory in an order irrelevant to the order of the instructions provided from the host.

A data processing system comprising a host, wherein the host comprises:

• address map memory configured to store a plurality of addresses that belong to a first range for instructing a memory operation to be performed on a memory device and a plurality of addresses that belong to a second range for instructing a processing operation to be performed using data read from a selected memory bank among memory banks of a memory of the memory device;
• and
• a memory interface configured to store an instruction associated with the memory operation and at least one other instruction in an instruction memory of the memory device while a mode of the memory device is an instruction loading mode,
• wherein the memory interface is configured to output an address including at least one bit having a bit value that belongs to the first range for setting the mode to a memory operation mode to perform a data access of the memory device,
• wherein the memory interface is configured to output the address including the at least one bit having the bit value that belongs to the second range for setting the mode to an operation processing mode to instruct that the processing operation be performed on an operand, output a write command to indicate the operand is to be received from the host, and output a read command to indicate the operand is to be read from the selected memory bank,
• wherein a part of the address that belongs to the second range different from the at least one bit indicates a position of the operand in the selected memory bank through a row address and a column address included in information of the part,
• wherein the setting of the mode to the memory operation mode or the operation processing mode occurs after storage of the instruction and the at least one other instruction completes during the instruction loading mode,
• wherein, in the instruction loading mode, the plurality of instructions are stored in the instruction memory in an order irrelevant to the order of the instructions provided from the host.