Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file

A computer program product for operating a processor for efficient use of a multi-level register file, the computer program product comprising:

• a non-transitory computer readable storage medium having computer usable program code embodied therewith, the computer usable program code configured to:
• receive an indication of a completed instruction, wherein the indication indicates a logical register mapped to a physical register in a first level register file;
• determine that metadata associated with the completed instruction indicates that maintaining a mapping of the logical register to the physical register in the first level register file and allowing data of the logical register to remain in the physical register in the first level register file will reduce performance of the processor;
• responsive to a determination that the metadata associated with the completed instruction indicates that maintaining the mapping of the logical register to the physical register in the first level register file and allowing the data of the logical register to remain in the physical register in the first level register file will reduce performance of the processor, write the data of the logical register to a physical register in a second level register file;
• determine whether an entry in a mapping structure indicates a mapping between the logical register and the physical register in the first level register file for the completed instruction;
• indicate in the entry that the entry is to be victimized first if the entry in the mapping structure indicates the mapping between the logical register and the physical register in the first level register file for the completed instruction;
• and
• avoid updating the mapping structure with the mapping between the logical register and the physical register in the first level register file to allow the physical register in the first level register file to be available if the mapping structure does not have an entry indicating the mapping between the logical register and the physical register in the first level register file for the completed instruction.

A processor comprising:

• a first level register file of physical registers;
• a second level register file of physical registers, wherein the first level register file is more efficiently accessed relative to the second level register file;
• and
• a register file mapper coupled with the first level register file and the second level register file, the register file mapper comprising:
• a mapping structure operable to host mappings between logical registers and the physical registers of the first level register file;
• a register file controller operable to determine, based on metadata associated with an instruction, whether to map a destination logical register of the instruction to one of the physical registers of the first level register file or to write data associated with the destination logical register to one of the physical registers of the second level register file, wherein the register file controller is further operable to update hardware counters responsive to at least one of referencing a logical register and casting out data from the first level register file to a lower level register file;
• and
• a register designated to host a value specifying a threshold that represents a high rate of thrashing for a thread.