Execution control of a multi-threaded, self-scheduling reconfigurable computing fabric

An apparatus, comprising:

• a configurable computation circuit;
• a plurality of synchronous network inputs coupled to the configurable computation circuit;
• a plurality of synchronous network outputs coupled to the configurable computation circuit;
• an asynchronous network input queue;
• an asynchronous network output queue;
• a configuration memory circuit coupled to the configurable computation circuit, to the plurality of synchronous network inputs, and to the plurality of synchronous network outputs, the configuration memory circuit comprising:
• a first instruction memory configured to store a first plurality of data path configuration instructions to configure a data path of the configurable computation circuit;
• and
• a second instruction memory configured to store a second plurality of data path configuration instructions or instruction indices for selection of a current data path configuration instruction of the first plurality of data path configuration instructions from the first instruction memory and for selection of a master synchronous network input of the plurality of synchronous network inputs for receipt of the current data path configuration instruction or instruction index from an adjacent configurable circuit;
• and
• a control circuit coupled to the configurable computation circuit, the control circuit comprising:
• a plurality of control registers configured to store a completion table having a plurality of thread identifiers and having a corresponding data completion count for each thread identifier of the plurality of thread identifiers;
• and
• a thread control circuit configured to queue a selected thread for execution when, for a thread identifier for the selected thread, of the plurality of thread identifiers, the corresponding data completion count has decremented to zero and the thread identifier is identified as a next thread.

An apparatus comprising:

• an asynchronous packet network;
• a synchronous network;
• and
• a plurality of configurable circuits arranged in an array, each configurable circuit of the plurality of configurable circuits comprising:
• one or more asynchronous inputs coupled to the asynchronous packet network:
• one or more asynchronous outputs coupled to the asynchronous packet network;
• a configurable computation circuit;
• a plurality of synchronous network inputs coupled to the configurable computation circuit;
• a plurality of synchronous network outputs coupled to the configurable computation circuit;
• a configuration memory coupled to the configurable computation circuit, to the plurality of synchronous network inputs, and to the plurality of synchronous network outputs, the configuration memory comprising:
• a first instruction memory configured to store a first plurality of data path configuration instructions to configure an internal data path of the configurable computation circuit;
• and
• a second instruction memory configured to store a second plurality of data path configuration instructions or instruction indices for selection of a current data path configuration instruction of the first plurality of data path configuration instructions from the first instruction memory and for selection of a master synchronous network input of the plurality of synchronous network inputs for receipt of the current data path configuration instruction or instruction index from another configurable circuit of the array;
• and
• a control circuit coupled to the configurable computation circuit, the control circuit comprising:
• a plurality of control registers configured to store a completion table having a plurality of thread identifiers and having a corresponding data completion count for each thread identifier of the plurality of thread identifiers;
• and
• a thread control circuit configured to self-schedule and queue a thread for execution when the corresponding data completion count, for a corresponding thread identifier of the plurality of thread identifiers, has decremented to zero to indicate completion of any data dependencies.