Multi-port register file for partial-sum accumulation

A process for storing accumulation data in a multi-port register file, comprising:

• disabling a write signal applied to a plurality of multi-bit registers of the multi-port register file during a partial-sum accumulation process;
• enabling the write signal applied to the plurality of multi-bit registers of the multi-port register file in response to a final accumulation result of the partial-sum accumulation process being available;
• and
• writing the final accumulation result to a selected one of the plurality of multi-bit registers of the multi-port register.

A processing element, comprising:

• logical circuitry for performing an accumulation process;
• and
• a multi-port register file, wherein the multi-port register file includes:
• a plurality of single-bit data registers for receiving and storing partial-sum data of the accumulation process;
• a read path coupled to an output of each of the plurality of data registers;
• a plurality of AND gates, wherein the output of each of the plurality of data registers is coupled to an input of a respective AND gate of the plurality of AND gates;
• an input gating signal coupled to another input of each of the plurality of AND gates;
• a plurality of multi-bit registers, wherein an output of each of the plurality of AND gates is coupled to each of the plurality of multi-bit registers;
• and
• a write disable circuit coupled to the input gating signal for disabling a write signal applied to each of the plurality of multi-bit registers.