Hardware-implemented universal floating-point instruction set architecture for computing directly with human-readable decimal character sequence floating-point representation operands

A universal floating-point Instruction Set Architecture (ISA) compute engine implemented entirely in hardware, said ISA compute engine comprising:

• a program memory;
• and
• hardware circuitry connected to the program memory, said hardware circuitry configured to compute directly with human-readable decimal character sequence floating-point representation operands using a single instruction per floating-point operation, the hardware circuitry comprising:
• a data memory having a write port and first and second read ports, said data memory configured to write data into the write port while simultaneously reading binary format operands or human-readable decimal character sequence floating-point representation operands from the first and second read ports;
• at least one fully pipelined convertToBinaryFromDecimalCharacter hardware conversion circuit connected to the data memory and having one or more inputs and an output, the convertToBinaryFromDecimalCharacter hardware conversion circuit being configured to:
• receive the binary format operands or human-readable decimal character sequence floating-point representation operands from the data memory,
• convert the received human-readable decimal character sequence floating-point representation operands, if any, to IEEE 754-2008 binary floating-point representations, and
• preserve the received binary format operands, if any, as unconverted binary format operands;
• a multistage instruction pipeline logic circuit configured to fetch, decode, and execute instructions from the program memory, wherein, a single instruction that specifies one or more read addresses in the data memory causes one or more operands to be set in-flight within the convertToBinaryFromDecimalCharacter hardware conversion circuit, wherein the instruction pipeline logic is configured to:
• simultaneously read from the first and/or second read ports of the data memory, at least one IEEE 754-2008 binary floating-point representation operand and/or at least one human-readable decimal character sequence floating-point representation operand residing at the one or more read addresses specified by the single instruction, and
• simultaneously write the one or more operands to the one or more inputs of the at least one fully pipelined convertToBinaryFromDecimalCharacter hardware conversion circuit;
• and
• at least one memory-mapped, fully pipelined, hardware floating-point operator connected in series with the output of the at least one convertToBinaryFromDecimalCharacter hardware conversion circuit, the at least one hardware floating-point operator automatically receiving the at least one IEEE 754-2008 binary floating-point representations and utilizing the received at least one IEEE 754-2008 binary floating-point representations as operands for use in the at least one hardware floating-point operator's computation when a destination address in the single instruction corresponds to the memory-map address of the at least one hardware floating-point operator, wherein results computed by the at least one hardware floating-point operator automatically spill into the data memory write port at the destination address specified by the single instruction.