Managing memory reliability in memory systems

A memory system comprising:

• a memory device comprising a plurality of blocks;
• and
• a memory controller coupled to the memory device and configured to maintain first parameter data of at least one first parameter associated with the blocks,
• wherein the memory device comprises an adjusted read level (ARL) circuit that is configured to determine at least one read voltage for a specified block in the blocks based on corresponding first parameter data for the specified block from the memory controller,
• wherein the memory controller is configured to:
• determine whether or not to enable an ARL determination for a read command;
• in response to determining to enable the ARL determination for the read command, send a specified command to the memory device, the specified command comprising ARL information for determining at least one adjusted read voltage for at least one block in the memory device, wherein the ARL information comprises:
• first parameter data of the at least one first parameter associated with the at least one block or ARL data for the at least one block, and
• wherein the memory device is configured to:
• in response to determining that the ARL information comprises the ARL data, set a control flag in the memory device to indicate the ARL determination based on the ARL data;
• store the ARL data in an internal memory of the memory device;
• and
• determine the at least one adjusted read voltage based on the ARL data stored in the internal memory of the memory device.

A memory device comprising:

• a memory cell array having a plurality of blocks;
• and
• circuitry coupled to the memory cell array, the circuitry comprising an adjusted read level (ARL) circuit and being configured to:
• receive a read command from a memory controller, the read command comprising address information of at least one block in the memory cell array;
• determine whether the read command comprises an indication for enabling adjusted read level (ARL) determination;
• in response to determining that the read command comprises the indication for enabling the ARL determination;
• determine at least one adjusted read voltage for the at least one block using the ARL circuit;
• and
• execute a read operation based on the at least one adjusted read voltage according to the read command,
• wherein the ARL circuit comprises:
• a first internal memory configured to store ARL parameters received from the memory controller;
• a second internal memory configured to store ARL data received from the memory controller;
• and
• an ARL control circuit comprising:
• a control flag register configured to store an indication of ARL determination from one of the ARL parameters and the ARL data, and
• an ARL calculation circuit configured to calculate the at least one adjusted read voltage for the at least one block based on the one of the ARL parameters and the ARL data according to the indication in the control flag register.

A memory system comprising:

• a memory device comprising multiple planes having a plurality of blocks;
• and
• a memory controller coupled to the memory device and configured to send a read command to the memory device, the read command comprising address information of at least one block in the memory device, the at least one block comprising a respective block in each plane of the planes,
• wherein the memory device comprises circuitry configured to:
• determine whether the read command comprises an indication for enabling adjusted read level (ARL) determination;
• in response to determining that the read command comprises the indication for enabling the ARL determination, determine at least one adjusted read voltage for the at least one block by determining, for each of the respective blocks in the planes, a different corresponding adjusted read voltage;
• and
• execute a multi-plane read operation based on the at least one adjusted read voltage according to the read command.

A memory system comprising:

• a memory device comprising a plurality of blocks;
• and
• a memory controller coupled to the memory device and configured to send a read command to the memory device, the read command comprising address information of at least one block in the memory device,
• wherein the memory device is configured to:
• determine whether the read command comprises an indication for enabling adjusted read level (ARL) determination;
• in response to determining that the read command comprises the indication for enabling the ARL determination, determine at least one adjusted read voltage for the at least one block;
• and
• execute:
• a read operation based on the at least one adjusted read voltage according to the read command, and
• wherein the read command comprises a prefix cycle code and a command cycle code, and wherein one of the prefix cycle code and the command cycle code is configured to include the indication for enabling the ARL determination.