NOR flash memory apparatus and recover and read method thereof
AssigneeWinbond Electronics Corp.
InventorKoying Huang
Life of this patent
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Abstract
A NOR flash memory apparatus and a recover and read method for the NOR flash memory apparatus are described. The recover and read method includes: operating a power-up process on the NOR flash memory apparatus during a power-up time period; operating a power-up reading operation and reading a mark bit of a memory block of the flash memory apparatus during a reading time period after the power-up time period; and, applying a negative voltage to a plurality of un-selected word lines for the power-up reading operation to operate without leakage current from bit lines of the memory block being caused and therefore to operate normally without causing mistakes.
Claims20
A recover and read method, adapted for a NOR flash memory apparatus, comprising:
- operating a power-up process on the NOR flash memory apparatus to raise a voltage level of an operation power voltage from 0V to a threshold voltage during a first time period;
- and
- operating a power-up reading operation during a second time period after the first time period when a logic level of a power on reading signal equals to a specific logic level, wherein the power-up reading operation comprises:
- reading a mark bit that is stored in a memory block in a memory array of the flash memory apparatus during the second time period;
- and
- in response to determining that the mark bit indicates the memory block has not been erased, applying a negative voltage to a plurality of un-selected word lines during a third time period,
- wherein the second time period is earlier than the third time period and an end time of the second time period is earlier than a finish time point of the power-up process, wherein the voltage level of the operation power voltage is raised to a target voltage level at the finish time point.
A NOR flash memory apparatus, comprising:
- at least one memory array each having at least one memory block;
- a memory controller, coupled to the at least one memory block, the memory controller being configured to:
- operate a power-up process on the NOR flash memory apparatus to raise a voltage level of an operation power voltage from 0V to a threshold voltage during a first time period;
- and
- operate a power-up reading operation during a second time period after the first time period when a logic level of a power on reading signal equals to a specific logic level, wherein the power-up reading operation comprises:
- reading a mark bit that is stored in the memory block of the flash memory apparatus during the second time period;
- and
- in response to determining that the mark bit indicates the memory block has not been erased, applying a negative voltage to a plurality of un-selected word lines during a third time period,
- wherein the second time period is earlier than the third time period and an end time of the second time period is earlier than a finish time point of the power-up process, wherein the voltage level of the operation power voltage is raised to a target voltage level at the finish time point.
Dependencies are inferred from the claim text.