Memory device interface and method
AssigneeMicron Technology, Inc.
InventorBrent Keeth
Life of this patent
Estimating the term…
Abstract
Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.
Claims24
A memory module, comprising:
- a first stack of at least nine memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module;
- a memory controller configured to receive memory access commands and to access memory locations of the first stack, wherein the memory controller is configured to store error correction code (ECC) information on a first memory die of the at least nine memory dies, and wherein the first memory die is not one of the four pairs of memory dies;
- and
- a substrate configured to route connections between external terminations of the first stack of memory die and the memory controller.
An apparatus, comprising:
- a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks;
- a memory controller configured to receive memory access commands and to access memory locations of the first stack;
- and
- a substrate configured to route connections between external terminations of the first stack of memory die and the memory controller;
- a buffer die coupled to the substrate, the buffer die including a host device interface, and a memory interface coupled to the first stack;
- and
- circuitry in the buffer die, configured to operate the host interface at a first data speed, and to operate the memory interface at a second data speed, slower than the first data speed.
A method, comprising:
- storing information at memory cells of at least eight memory devices in a stack;
- organizing the information across four ranks of memory cells, wherein each rank of the four ranks is assigned to at least two of the at least eight memory devices;
- and
- storing error correction code (ECC) information on memory cells of a ninth memory device of the stack, wherein the ninth memory device is in addition to the at least eight memory devices.
Dependencies are inferred from the claim text.