Matrix storage method, matrix access method, apparatus and electronic device

A matrix access method, applied to an electronic device comprising at least one processor and an off-chip storage which is connected to and in communication with the at least one processor, wherein the matrix is stored in an off-chip storage using a matrix storage method, comprising:

• dividing a matrix into a plurality of data blocks with a preset segmentation granularity of N rows×M columns, at least one of N and M is greater than 1;
• wherein the plurality of data blocks comprises at least one first data block of N rows×M columns;
• if the column number of the matrix is not an integer multiple of M, the plurality of data blocks further comprises at least one second data block of N rows×P columns, the second data block is aligned with an adjacent row of first data block, and P is less than M;
• storing the data in each of the first data blocks continuously in the off-chip storage, and storing the data in each of the second data blocks continuously in the off-chip storage,
• wherein the off-chip storage comprises a plurality of storage channels, and the segmentation granularity is an integral multiple of a storage granularity of each storage channel;
• the matrix access method comprising:
• receiving an access request for the matrix, wherein the access request comprises access parameters of the matrix;
• if the data block corresponding to the access parameter comprises a complete first data block or a complete second data block, reading the data of the data block from the off-chip storage;
• if the data block corresponding to the access parameter comprises an incomplete first data block or an incomplete second data block, reading the data of the data block from the off-chip storage is prohibited.