System on chip for reducing wake-up time, method of operating same, and computer system including same
AssigneeSamsung Electronics Co., Ltd.
InventorHee Dong Shin
Life of this patent
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Abstract
A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.
Claims9
A system on chip (SoC) comprising:
- a first power domain including a first memory;
- a second power domain including a second memory;
- a read-only memory (ROM) configured to store a first boot loader;
- and
- a power management unit (PMU) configured to independently control a cut-off and supplying of an operating voltage to the first power domain and the second power domain,
- wherein, the first memory and the second memory are configured to store a second boot loader and a third boot loader, respectively.
Dependencies are inferred from the claim text.