Method for reducing line-end space in integrated circuit patterning
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJing-Huei Huang, Ya-Wen Chiu, Lun-Kuang Tan
Life of this patent
Estimating the term…
Loading patent…
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJing-Huei Huang, Ya-Wen Chiu, Lun-Kuang Tan
Estimating the term…
A method includes forming a resist pattern, the resist pattern having trenches oriented lengthwise along a first direction and separated by resist walls along both the first direction and a second direction perpendicular to the first direction. The method further includes loading the resist pattern into an ion implanter so that a top surface of the resist pattern faces an ion travel direction, and tilting the resist pattern so that the ion travel direction forms a tilt angle with respect to an axis perpendicular to the top surface of the resist pattern. The method further includes rotating the resist pattern around the axis to a first position; implanting ions into the resist walls with the resist pattern at the first position; rotating the resist pattern around the axis by 180 degrees to a second position; and implanting ions into the resist walls with the resist pattern at the second position.
A method, comprising:
A method, comprising:
A method, comprising:
Dependencies are inferred from the claim text.