Device and method for monitoring data and timing signals in integrated circuits

A method, comprising:

• outputting a first signal from a flip-flop having a first latch and a second latch connected in series;
• outputting a second signal from a third latch having an input coupled to an output of the first latch;
• receiving the first and second signals at a logic gate;
• and
• generating, with the logic gate, a third signal indicative of whether there is risk of a timing fault related to the flip-flop based on the first and second signals.

An integrated circuit, comprising:

• a flip-flop including:
• a first latch;
• a midpoint node;
• a second latch coupled to the first latch at the midpoint node;
• and
• a third latch coupled to the midpoint node of the flip-flop and including an output;
• and
• a logic gate including;
• a first input coupled to the midpoint node of the flip-flop;
• a second input coupled to the output of the third latch;
• and
• an output configured to output a signal indicating risk of a timing failure in the flip-flop.