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US 11,635,463 B1Granted
System and methods for IJTAG reduced access time in a hierarchical design
AssigneeMarvell Asia Pte Ltd
InventorsKrishnaraj Venkatesan, Raghuveer Shivaraj
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Abstract
A system includes a test access port (TAP) configured to provide internal joint test action group (IJTAG) access to one or more test data registry (TDR). The system further includes a plurality of hierarchical electronic components, wherein each hierarchical electronic component includes a de-asserted segment inserted bit (D-SIB) register, an asserted segment inserted bit (A-SIB) register, and a TDR associated with the D-SIB register. Each D-SIB register is configured to prevent access to its associated TDR when a reset signal is asserted and each A-SIB register is configured to provide access to its subsequent A-SIB register or D-SIB register coupled thereto when the reset signal is asserted.
Claims25
A hardware-based system, comprising:
- a test access port (TAP) configured to provide internal joint test action group (IJTAG) access to one or more test data registries (TDRs);
- a first hierarchical electronic components coupled to the TAP, wherein the first hierarchical electronic components includes a first de-asserted segment inserted bit (D-SIB) register, a first asserted segment inserted bit (A-SIB) register, and a first TDR of the one or more TDRs, wherein the first D-SIB register is coupled to the first TDR, and wherein the first A-SIB register is coupled to a second hierarchical electronic components;
- said second hierarchical electronic components coupled as a child to the first hierarchical electronic components, wherein the second hierarchical electronic components includes a second D-SIB register, a second A-SIB register, and a second TDR of the one or more TDRs, wherein the second D-SIB register is coupled to the second TDR, and wherein the second A-SIB register is coupled to a third hierarchical electronic components;
- and
- the third hierarchical electronic components coupled as a child to the second hierarchical electronic components, wherein the third hierarchical electronic components includes a third D-SIB register, a third A-SIB register, and a third TDR, wherein the third D-SIB register is coupled to the third TDR,
- wherein in a first iteration each D-SIB register is configured to prevent access to its associated TDR when a reset signal is asserted and wherein each A-SIB register is asserted.
3 more elements
A hardware-based system, comprising:
- a test access port (TAP) configured to provide internal joint test action group (IJTAG) access to one or more test data registry (TDR);
- and
- a plurality of hierarchical electronic components, wherein each hierarchical electronic component includes a de-asserted segment inserted bit (D-SIB) register, an asserted segment inserted bit (A-SIB) register, and a TDR associated with the D-SIB register,
- wherein in a first iteration each D-SIB register is configured to prevent access to its associated TDR when a reset signal is asserted and wherein each A-SIB register is asserted.
1 more element
A method comprising:
- receiving an asserted reset signal at a plurality of hierarchical electronic components;
- in response to receiving the asserted reset signal, preventing access to every test data register (TDR) within the plurality of hierarchical electronic components;
- in response to receiving the asserted reset signal, asserting all hierarchical electronic components of the plurality of hierarchical electronic components within a same iteration;
- receiving a de-asserted reset signal;
- in response to the de-asserted reset signal, programming one or more TDRs within the plurality of hierarchical electronic components;
- after the programming, asserting every hierarchical electronic components of the plurality of hierarchical electronic components while preventing access to TDRs of a hierarchical electronic components that remain unprogrammed;
- and
- reading out data from the asserted hierarchical electronic components in one iteration.
5 more elements
A hardware-based system, comprising:
- a means for receiving an asserted reset signal at a plurality of hierarchical electronic components;
- a means for preventing access to every test data register (TDR) within the plurality of hierarchical electronic components in response to receiving the asserted reset signal;
- a means for asserting all hierarchical electronic components of the plurality of hierarchical electronic components within a same iteration in response to receiving the asserted reset signal;
- a means for receiving a de-asserted reset signal;
- a means for programming one or more TDRs within the plurality of hierarchical electronic components in response to the de-asserted reset signal;
- a means for asserting every hierarchical electronic components of the plurality of hierarchical electronic components while preventing access to TDRs of a hierarchical electronic components that remain unprogrammed, after the programming;
- and
- a means for reading out data from the asserted hierarchical electronic components in one iteration.
5 more elements
Dependencies are inferred from the claim text.