Library cell modeling for transistor-level test pattern generation

A system comprising:

• a memory system configured to store computer-executable instructions;
• and
• a computing system, in response to execution of the computer-executable instructions, is configured to:
• convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell;
• generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell;
• divide the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns;
• perform an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to determine which of the test patterns in the second subset of the test patterns enables detection of the target defects when injected into the transistor-level model of the library cell;
• and
• determine to skip performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.

An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

• converting a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell;
• generating test patterns configured to enable detection of target defects injected into the switch-level model of the library cell;
• dividing the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns;
• performing an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to determine which of the test patterns in the second subset of the test patterns enables detection of the target defects when injected into the transistor-level model of the library cell;
• and
• determining to skip performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.