Multi-rate digital sensor synchronization
AssigneeHarman Becker Automotive Systems GmbH
InventorsYuliu Cao, Juergen Zollner, Franz Lorenz, Bin Gao, Shiyu Chen, Tingting Zhou, Alex Lee
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Abstract
A system and method for multi-rate synchronization of a digital sensor that provides a digital sensor output signal and a processor arrangement that processes the digital sensor output signal according to a processing algorithm and that provides a processor output signal, including operating the digital sensor to provide the digital sensor output signal with a first sample rate, and operating the processor arrangement to provide a processor output signal with a second sample rate. The second sample rate is an integer multiple of the first sample rate.
Claims14
A method for multi-rate synchronization of a digital sensor that provides a digital sensor output signal and a processor arrangement that processes the digital sensor output signal according to a processing algorithm and that provides a processor output signal, the method comprising the steps of:
- operating the digital sensor to provide the digital sensor output signal with a first sample rate;
- in a processor arrangement that has a main processor and a host processor, the processor arrangement is separate from a transceiver of the digital sensor, the main processor has a second sample rate that is an integer multiple of the first sample rate;
- generating a trigger signal in the host processor at the first sample rate, the trigger signal triggers polling of the digital sensor output signal when a new sample of the digital sensor output signal is available;
- forwarding the trigger signal to the digital sensor to synchronize polling of the digital sensor output signal at the first sample rate;
- forwarding the trigger signal to the main processor;
- in response to receiving the trigger signal from the host processor, the main processor samples the digital sensor output signal using both the first and the second sample rates;
- synchronizing, in the main processor, the digital sensor output signal of the first sample rate with the digital signal sensor output signal of the second sample rate thereby generating a processor output signal at the second sample rate;
- and
- outputting the processor output signal at the second sample rate.
A system for multi-rate synchronization of a digital sensor that is configured to provide a digital sensor output signal and a processor arrangement that is configured to process the digital sensor output signal according to a processing algorithm and to provide a processor output signal, wherein:
- the digital sensor is further configured to provide the digital sensor output signal with a first sample rate;
- the processor arrangement is separate from a transceiver of the digital signal processor, the processor arrangement has a main processor and a host processor, the main processor has a second sample rate that is an integer multiple of the first sample rate;
- a trigger signal is generated in the host processor of the processor arrangement when a new sample of the digital sensor output signal is available;
- the trigger signal is forwarded to the digital sensor to trigger polling of the digital sensor output signal;
- the trigger signal is forwarded to the main processor to trigger sampling of the digital sensor output signal using the first and second sample rates;
- the main processor of the processor arrangement synchronizes the digital sensor output signal using both the first and the second sample rates thereby generating a processor output signal;
- and
- the processor output signal is output by the main processor using the second sample rate.
Dependencies are inferred from the claim text.