Arithmetic logic unit design in column analog to digital converter with shared gray code generator for correlated multiple samplings

An imaging system, comprising:

• a pixel array including a plurality of pixel circuits arranged into rows and columns, wherein each one of the plurality of pixel circuits is coupled to generate an analog image data signal in response to incident light;
• control circuitry coupled to the pixel array to control operation of the pixel array;
• and
• a readout circuit coupled to the pixel array through a plurality of column bit lines, wherein the readout circuit comprises:
• a plurality of comparators, wherein each one of the plurality of comparators is coupled to receive a ramp signal, wherein each one of the plurality of comparators is further coupled to a respective one of a plurality of column bit lines to receive a respective analog image data signal, wherein each one of the plurality of comparators is coupled to generate a respective comparator output in response to a comparison of the respective analog image data signal and the ramp signal;
• a Gray code (GC) generator coupled to generate GC outputs;
• and
• a plurality of arithmetic logic units (ALUs), wherein each one of the plurality of ALUs is coupled to receive the GC outputs, wherein each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output, wherein each one of the plurality of ALUs comprises:
• a front end latch stage coupled to the GC generator to latch the GC outputs of the GC generator in response to the respective comparator output;
• a signal latch stage coupled to latch outputs of the front end latch stage in response to a signal latch enable signal;
• a GC to binary stage coupled to generate a binary representation of the GC outputs latched in the signal latch stage;
• an adder stage including first inputs and second inputs, wherein the first inputs of the adder stage are coupled to receive outputs of the GC to binary stage, wherein outputs of the adder stage are generated in response to the first inputs and the second inputs of the adder stage;
• a pre-latch stage coupled to latch outputs of the adder stage in response to a pre-latch enable signal;
• and
• a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal, wherein the second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.