Clock synthesizer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorWei Shuo Lin
Life of this patent
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Abstract
A clock synthesizer is provided. The Clock synthesizer includes a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer stores the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit receives the clock signal from the clock buffer, adjusts a duty cycle of the clock signal to substantially equal to 50%, performs phase interpolation on the clock signal, and provides the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.
Claims20
A clock synthesizer comprising:
- a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal;
- a clock buffer connected to the PLL, wherein the clock buffer is configured to store the clock signal;
- and
- a Duty Cycle Controller and Phase Interpolator (DCCPI) circuit connected to the clock buffer, wherein the DCCPI circuit comprises a phase interpolator and a voltage/current alternator, and wherein:
- the phase interpolator is configured to:
- receive the clock signal from the clock buffer, and
- perform phase interpolation on the clock signal, and
- the voltage/current alternator is configured to:
- adjust a duty cycle of the clock signal based on a difference between an average Direct Current (DC) voltage value of the clock signal and an average DC voltage value of an inverted clock signal, and
- provide the clock signal as an output after adjusting the duty cycle.
A clock synthesizer comprising:
- a Digital Control Delay Line (DCDL) circuit;
- a Duty Cycle Controller and Phase Interpolator (DCCPI) circuit connected to the DCDL circuit, wherein the DCCPI circuit is configured to adjust a duty cycle of an input clock signal and provide an output clock signal comprising duty cycle adjusted input clock signal;
- a replica circuit connected to the DCCPI circuit, wherein the replica circuit is operative to replicate the output clock signal and provide a replica clock signal;
- a phase detection circuit connected to the replica circuit, wherein the phase detection circuit is operative to:
- compare the replica clock signal with a reference clock signal, and
- provide, to the DCCPI circuit, a voltage signal that represents a difference in phase between the replica clock signal and the reference clock signal, and wherein the DCCPI circuit is operative to adjust a duty cycle of the clock signal and interpolate a phase value of the clock signal based on the difference in the phase between the replica clock signal with the reference clock signal.
A method of synthesizing clock, the method comprising:
- interpolating, by a phase interpolator, a phase value of an input clock signal to account for a time delay in distribution of a clock signal associated with the input clock signal;
- providing, by the phase interpolator, the clock signal associated with the input clock signal;
- determining, by an error amplifier connected to the phase interpolator, a difference between a Direct Current (DC) voltage value of the clock signal and a DC voltage value of an inverted clock signal;
- and
- adjusting, by a voltage current alternator connected to the error amplifier, a duty cycle of the clock signal based on the determined difference between the DC voltage value of the clock signal and the DC voltage value of the inverted clock signal to substantially equal to 50%.
Dependencies are inferred from the claim text.