Operational amplifier
AssigneeSTMicroelectronics (Grenoble 2) SAS
InventorsPhilippe Pignolo, Pawel Fiedorow, Vincent Rabary
Life of this patent
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Abstract
A differential pair for an input stage includes two identical branches in parallel, each branch including a first MOS transistor and a second MOS transistor arranged in series, wherein the first transistor and the second transistor have a channel of the same type, and wherein each of the first transistor and the second transistor has a gate coupled to the same corresponding input of the differential pair and a circuit configured to apply to each of the first transistors a potential difference between a source and a channel-forming region of the first transistor.
Claims21
A differential pair for an input stage comprising:
- two identical branches in parallel, each branch comprising a first MOS transistor and a second MOS transistor arranged in series, wherein the first transistor and the second transistor have a channel of the same type, and wherein each of the first transistor and the second transistor has a gate coupled to the same corresponding input of the differential pair;
- and
- a circuit configured to apply to each of the first transistors a potential difference between a source and a channel-forming region of the first transistor,
- wherein a dimension ratio of each first transistor is X times larger than a dimension ratio of each second transistor and X is larger than 1.
A differential pair for an input stage comprising:
- two identical branches in parallel, each branch comprising a first MOS transistor and a second MOS transistor arranged in series, wherein the first transistor and the second transistor have a channel of the same type, and wherein each of the first transistor and the second transistor has a gate coupled to the same corresponding input of the differential pair;
- and
- a circuit configured to apply to each of the first transistors a potential difference between a source and a channel-forming region of the first transistor,
- wherein the first transistor in each branch has a source coupled to a first end of the branch,
- wherein the second transistor in each branch has a drain coupled to a second end of the branch by an active load of the branch,
- wherein the first ends of the branches are coupled to a first node by a current source, the first node configured to be at a first DC voltage,
- wherein the second ends of the branches are coupled to a second node configured to be at a second DC voltage,
- wherein the active load comprises a resistor in series with a third MOS transistor having a channel of a type opposite to that of the first and second transistors,
- wherein the resistor is coupled to the second end of the branch and a drain of the third transistor is coupled to a drain of the second transistor of the branch, the third MOS transistors being a mirror of a fourth MOS transistor and the third and fourth MOS transistors being the same.
An operational amplifier comprising:
- an input stage comprising:
- a first differential pair comprising:
- two identical branches in parallel, each branch comprising a first MOS transistor and a second MOS transistor arranged in series, wherein the first transistor and the second transistor have a channel of the same type, and wherein each of the first transistor and the second transistor has a gate coupled to the same corresponding input of the first differential pair;
- and
- a circuit configured to apply to each of the first transistors a potential difference between a source and a channel-forming region of the first transistor,
- wherein the first and second transistors of the first differential pair have a P channel;
- and
- a second differential pair connected in parallel with the first differential pair, the second differential pair being of the same construction as the first differential pair,
- wherein a first transistor and a second transistor of the second differential pair have an N channel, and
- wherein the operational amplifier is a rail-to-rail type amplifier.
Dependencies are inferred from the claim text.