Low temperature polycrystalline semiconductor device and manufacturing method thereof
AssigneeYing Hong
InventorYing Hong
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Abstract
A semiconductor device include a substrate, a buffer layer formed on the substrate, a channel layer formed by an intrinsic polycrystalline silicon layer on the buffer layer, polycrystalline source and drain by non-intrinsic silicon formed on both sides of the polycrystalline silicon layer, a source electrode and a drain electrode formed on the polycrystalline source and the drain, a gate electrode corresponding to the channel layer, and an NiSi2 contact layer located between the source and the source electrode and between the drain and the drain electrode.
Claims2
A semiconductor device manufactured by a method of manufacturing a semiconductor device, the method comprising:
- forming a buffer layer of an insulating material on a substrate;
- forming a seed layer of catalyst material containing Ni on the buffer layer;
- forming, on the buffer layer, an amorphous intrinsic silicon layer for forming a channel;
- forming, on the amorphous intrinsic silicon layer, a non-intrinsic silicon layer for forming a source and/or drain;
- forming a metal layer on the non-intrinsic silicon layer;
- performing metal induced crystallization (MIC) process producing NiSi2 by catalytic reaction of Ni and Si for crystallization of the amorphous intrinsic silicon layer and the amorphous non-intrinsic silicon layer, and activation of the amorphous non-intrinsic silicon layer to form a conductive area, and forming a contact layer by the NiSb being reached between the conductive area and the metal layer while the crystallization is progressed;
- the semiconductor device comprising:
- a substrate;
- a buffer layer formed on the substrate;
- a channel layer formed by an intrinsic polycrystalline silicon layer on the buffer layer;
- polycrystalline source and drain by non-intrinsic silicon formed on both sides of the polycrystalline silicon layer;
- a source electrode and a drain electrode formed on the polycrystalline source and the drain;
- a gate electrode corresponding to the channel layer;
- and
- an NiS2 contact layer located between the source and the source electrode and between the drain and the drain electrode;
- wherein the non-intrinsic polycrystalline source and drain comprise:
- a first non-intrinsic silicon layer contacting both sides of the channel layer;
- and
- a second non-intrinsic silicon layer provided on the first non-intrinsic silicon layer,
- wherein:
- the first non-intrinsic silicon layer further extends toward the gate than the second non-intrinsic silicon layer to form a lightly doped drain (LDD).
Dependencies are inferred from the claim text.