System, method, and apparatus for SRIS mode selection for PCIe
AssigneeIntel Corporation
InventorsDavid J. Harriman, Debendra Das Sharma, Daniel S. Froelich, Sean O. Stalley
Life of this patent
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Abstract
Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.
Claims21
An apparatus comprising:
- a first device comprising:
- a port to couple to a second device via a link;
- and
- control logic to:
- determine a data rate supported by the port for data transmissions on the link;
- determine a clocking architecture supported by the port for the determined data rate;
- identify data rate information in a Peripheral Component Interconnect Express (PCIe) link capabilities 2 register, and
- send information across the link using the determined data rate and the determined clocking architecture;
- wherein the data rate information indicates that the port supports the clocking architecture at the determined data rate, and
- wherein the data rate comprises 32 gigatransfers per second (GT/s)
- the first device to send information to the second device via the link using the clocking architecture at the data rate of 32 GT/s.
A method comprising:
- identifying a data rate supported by a port of a first device, wherein the port couples the first device to a second device over a link, and the link is compliant with a Peripheral Component Interconnect Express (PCIe)-based protocol;
- determining that the port is to operate using a separate reference clock with independent spread spectrum clocking (SRIS) architecture;
- determining a data rate supported by the port using the SRIS architecture;
- identifying a bit in a PCIe link capabilities 2 register corresponding to the data rate supported by the port using SRIS;
- and
- sending information across the link using the determined data rate and the determined clocking architecture;
- wherein identifying the data rate supported by the port for data transmissions comprising identifying that the port supports 32 gigatransfers per second (GT/s) from bit 4 of a supported link speeds vector of a link capabilities 2 register.
A system comprising:
- a host device comprising a first port to support a link;
- and
- an endpoint device comprising a second port to support the link, wherein the host device couples to the endpoint device via the link,
- wherein the host device comprises protocol circuitry to:
- determine a data rate supported by the first port for data communication on the link;
- determine that a separate reference clock with independent spread spectrum clocking (SRIS) architecture is supported by the first port for the data rate;
- identify first data rate information in a host device link capabilities register to indicate that the first port supports the clocking architecture at the data rate;
- identify second data rate information in a link control register to indicate that the second port supports the clocking architecture at the data rate;
- send information across the link using the determined data rate and the determined clocking architecture;
- wherein the data rate comprises 32 gigatransfers per second (GT/s) and the protocol circuitry is to determine that the first port can support the SRIS architecture at the 32 GT/s data rate base on information in bit 4 of a SKP ordered set reception supported speeds vector of a link capabilities 2 register.
Dependencies are inferred from the claim text.