Chip testing apparatus and system with sharing test interface
AssigneeWinbond Electronics Corp.
InventorsChih-Chiang Lai, Cheng-Ching Huang
Life of this patent
Estimating the term…
Abstract
A chip testing apparatus and system suitable for performing testing on multiple chips in a chip cluster are provided. The chip testing apparatus includes a signal interface and a test design circuit. The signal interface transmits an input signal and multiple driving signals in parallel from a test equipment to each of the chips. The test design circuit receives multiple output signals from the chips through the signal interface and serially outputs a test data to the test equipment according to the output signals.
Claims19
A chip testing apparatus, suitable for testing a plurality of chips in a chip cluster, the chip testing apparatus comprising:
- a signal interface, coupled to the plurality of chips in the chip cluster, wherein the signal interface transmits an input signal and a plurality of driving signals in parallel from a test equipment to each of the chips;
- and
- a test design circuit, coupled to the signal interface, wherein the test design circuit receives a plurality of output signals from the plurality of chips through the signal interface and serially outputs a test data to the test equipment according to the plurality of output signals, wherein the test design circuit serially transmits the plurality of output signals sequentially serving as the test data to the test equipment through the signal interface.
A chip testing system, suitable for testing a plurality of chips in a chip cluster, the chip testing apparatus comprising:
- a signal interface, coupled to the plurality of chips in the chip cluster, wherein the signal interface transmits an input signal and a plurality of driving signals in parallel from a test equipment to each of the chips;
- and
- a test design circuit, coupled to the signal interface, wherein the test design circuit receives a plurality of output signals from the plurality of chips through the signal interface and serially outputs a test data to the test equipment according to the plurality of output signals,
- wherein the signal interface comprises a buffer circuit, coupled to each of the chip and the test design circuit, wherein the buffer circuit transmits the plurality of output signals outputted from the plurality of chips in parallel to the test design circuit in response to a plurality of output enable signals and the test design circuit serially transmits the plurality of output signals sequentially serving as the test data to the input output pad in response to a clock signal in the driving signals.
Dependencies are inferred from the claim text.