Memories for receiving or transmitting voltage signals

A memory, comprising:

• an array of memory cells;
• a register configured to generate a first voltage signal representing data values stored in memory cells of the array of memory cells;
• a current generator comprising a first input configured to receive the first voltage signal, comprising a second input configured to receive a second voltage signal, comprising a first output, and comprising a second output;
• a first inverter comprising an input connected to the first output of the current generator, and comprising an output;
• a second inverter comprising an input connected to the second output of the current generator, and comprising an output;
• a first resistance comprising a first end connected to the input of the first inverter, and comprising a second end connected to the output of the first inverter;
• a second resistance comprising a first end connected to the input of the second inverter, and comprising a second end connected to the output of the second inverter;
• a third inverter comprising an input connected to the output of the first inverter, and comprising an output connected to the output of the second inverter;
• a fourth inverter comprising an input connected to the output of the second inverter, and comprising an output connected to the output of the first inverter;
• wherein the current generator is configured to generate a current source at its first output and a current sink at its second output in response to a voltage level received at its first input being higher than a voltage level received at its second input;
• and
• wherein the current generator is configured to generate a current source at its second output and a current sink at its first output in response to a voltage level received at its second input being higher than a voltage level received at its first input.

A memory, comprising:

• an array of memory cells;
• input/output (I/O) control circuitry configured to receive a first voltage signal from an external device representing data for storage to the array of memory cells;
• and
• a register configured to receive a second voltage signal from the I/O control circuitry representing the data for storage to the array of memory cells;
• wherein the I/O control circuitry comprises an input buffer comprising:
• a first stage comprising:
• a first input configured to receive the first voltage signal;
• a second input configured to receive a third voltage signal;
• a first output;
• and
• a second output;
• wherein the first stage of the input buffer is configured to generate a current source at its first output and to generate a current sink at its second output in response to the first voltage signal being higher than the third voltage signal;
• and
• wherein the first stage of the input buffer is configured to generate a current sink at its first output and to generate a current source at its second output in response to the first voltage signal being lower than the third voltage signal;
• and
• a second stage comprising:
• a first input connected to the first output of the first stage of the input buffer;
• a second input connected to the second output of the first stage of the input buffer;
• a first voltage signal node connected to the first input of the second stage of the input buffer through a first resistance;
• a third voltage signal node connected to the second input of the second stage of the input buffer through a second resistance;
• a first inverter connected in parallel with the first resistance;
• a second inverter connected in parallel with the second resistance;
• a third inverter comprising an input connected to an output of the first inverter, and comprising an output connected to an output of the second inverter;
• and
• a fourth inverter comprising an input connected to the output of the second inverter, and comprising an output connected to the output of the first inverter.