Technologies for providing hardware resources as a service with direct resource addressability
AssigneeIntel Corporation
InventorsRaghu Kondapalli, Alexander Bachmutsky, Francesc Guim Bernat, Ned M. Smith, Kshitij A. Doshi
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Abstract
Technologies for providing hardware resources as a service with direct resource addressability are disclosed. According to one embodiment of the present disclosure, a device receives a request to access a destination accelerator device in an edge network, the request specifying a destination address assigned to the destination accelerator device. The device determines, as a function of the destination address, a location of the destination accelerator device and sends the request to the destination accelerator device.
Claims24
An apparatus comprising:
- memory;
- instructions in the apparatus;
- and
- processor circuitry to execute the instructions to:
- determine a location of a destination accelerator device in an edge network in response to a request indicative of a destination address assigned to the destination accelerator device;
- and
- send the request to the destination accelerator device after:
- (1) a determination that the request is valid based on an access control policy, and (2) a determination of an availability of the destination accelerator device.
At least one machine-readable storage device or storage disc comprising instructions that, when executed by at least one processor, cause a compute device to at least:
- determine a location of a destination accelerator device in an edge network in response to a request indicative of a destination address assigned to the destination accelerator device;
- and
- send the request to the destination accelerator device after:
- (1) a determination that the request is valid based on an access control policy, and (2) a determination of an availability of the destination accelerator device.
An apparatus comprising:
- at least one memory;
- and
- processor circuitry including one or more of:
- at least one of a central processor unit, a graphic processor unit or a digital signal processor, the at least one of the central processor unit, the graphic processor unit or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a result of the one or more first operations, the instructions in the apparatus;
- a Field Programmable Gate Array (FPGA), the FPGA including first logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the first logic gate circuitry and interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations;
- or
- Application Specific Integrated Circuitry including second logic gate circuitry to perform one or more third operations;
- the processor circuitry to perform at least one of the first operations, the second operations or the third operations to:
- determine a location of a destination accelerator device in an edge network in response to a request indicative of a destination address assigned to the destination accelerator device;
- and
- send the request to the destination accelerator device after:
- (1) a determination that the request is valid based on an access control policy, and (2) a determination of an availability of the destination accelerator device.
Dependencies are inferred from the claim text.