Sensor-less circuits and related methods for back EMF zero crossing detection

A sensor-less detection circuit, comprising:

• a first voltage adjustment circuit configured for providing a first output voltage, at a first node, using one of a first input voltage, a second input voltage, or a third input voltage;
• a second voltage adjustment circuit configured for providing a second output voltage, at a second node, using at least two of the first input voltage, the second input voltage, or the third input voltage;
• and
• a differential amplifier having a first input coupled with the first node and a second input coupled with the second node and configured for providing a third output voltage at a third node;
• wherein the second voltage adjustment circuit comprises an internal virtual neutral point;
• wherein the first voltage adjustment circuit comprises a plurality of resistive voltage dividers;
• wherein the second voltage adjustment circuit comprises the plurality of resistive voltage dividers;
• and
• wherein the sensor-less detection circuit is configured to detect a zero crossing event of a three-phase motor.

A method of sensor-less detection of a zero crossing event of a three-phase motor, comprising:

• electrically coupling a first voltage adjustment circuit with a three-phase brushless direct current (BLDC) motor and, using one of a first input voltage, a second input voltage, or a third input voltage, providing a first output voltage at a first node using the first voltage adjustment circuit;
• electrically coupling a second voltage adjustment circuit with the BLDC motor and, using at least two of the first input voltage, the second input voltage, or the third input voltage, providing a second output voltage at a second node using the second voltage adjustment circuit;
• and
• electrically coupling a first input of a differential amplifier with the first node, electrically coupling a second input of the differential amplifier with the second node, and, using the differential amplifier, providing a third output voltage at a third node;
• wherein the first voltage adjustment circuit comprises a plurality of switches;
• wherein the first voltage adjustment circuit comprises a plurality of resistive voltage dividers;
• and
• wherein the second voltage adjustment circuit comprises an internal virtual neutral point.