Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip

A multi-chip package comprising:

• a first semiconductor integrated-circuit (IC) chip comprising a first silicon substrate, a plurality of first through silicon vias vertically in the first silicon substrate, an insulating layer on a bottom surface of the first silicon substrate, a plurality of first metal bumps at a bottom of the first semiconductor integrated-circuit (IC) chip, wherein a metal bump of the plurality of first metal bumps couples to a through silicon via of the plurality of first through silicon vias and extends, in a horizontal direction, under a bottom surface of the insulating layer, wherein the metal bump comprises a first copper layer having a thickness between 1 and 60 micrometers and protruding from the bottom surface of the insulating layer, a plurality of first transistors at a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme couples to the plurality of first through silicon vias and plurality of first transistors, wherein the first interconnection scheme comprises a first oxide-containing layer and plurality of first copper pads at a top of the first semiconductor integrated-circuit (IC) chip, wherein each of the plurality of first copper pads is in the first oxide-containing layer;
• a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip, wherein the second semiconductor integrated-circuit (IC) chip comprises a second silicon substrate at a top of the second semiconductor integrated-circuit (IC) chip, a plurality of second transistors at a bottom surface of the second silicon substrate and a second interconnection scheme under the second silicon substrate, wherein the second interconnection scheme couples to the plurality of second transistors, wherein the second interconnection scheme comprises a second oxide-containing layer and plurality of second copper pads at a bottom of the second semiconductor integrated-circuit (IC) chip, wherein each of the plurality of second copper pads is in the second oxide-containing layer, wherein a bottom surface of the second oxide-containing layer is bonded to and in contact with a top surface of the first oxide-containing layer, and a bottom surface of each of the plurality of second copper pads is bonded to and in contact with a top surface of one of the plurality of first copper pads, wherein the second semiconductor integrated-circuit (IC) chip couples to the first semiconductor integrated-circuit (IC) chip through the plurality of second copper pads and plurality of first copper pads;
• a sealing layer on the first semiconductor integrated-circuit (IC) chip and covering a sidewall of the second semiconductor integrated-circuit (IC) chip;
• an interconnection substrate under the first semiconductor integrated-circuit (IC) chip and joining the plurality of first metal bumps, wherein the interconnection substrate is across an edge of the first semiconductor integrated-circuit (IC) chip;
• and
• an underfill between the first semiconductor integrated-circuit (IC) chip and interconnection substrate, wherein the underfill contacts the bottom of the first semiconductor integrated-circuit (IC) chip, a top of the interconnection substrate and a sidewall of the first copper layer.