Hardware accelerator with analog-content addressable memory (a-CAM) for decision tree computation

A system for implementing a decision tree comprising:

• a hardware accelerator;
• a machine-readable medium storing instructions that, when executed by the hardware accelerator, causes the hardware accelerator to:
• access a decision tree, wherein the decision tree comprises of multiple paths and each path of the multiple paths comprises of a set of nodes, and wherein each node of the set of nodes is associated with a feature variable of multiple feature variables in the decision tree;
• combine for each path of the multiple paths, multiple nodes among the set of nodes with a same feature variable into a combined single node, and wherein each combined single node is associated with a feature variable of the multiple feature variables;
• substitute a wildcard value for a feature variable not being evaluated in the set of the nodes of the each path of the multiple paths in the decision tree;
• map, each combined single node associated with each feature variable of the multiple feature variables in each path to a corresponding column of an analog Content Addressable Memory (a-CAM) array, wherein the a-CAM array comprises of a-CAM cells, and wherein each a-CAM cell stores at least one of an analog range or an analog threshold value associated with a given feature variable of the multiple feature variables, and wherein the given feature variable matches the feature variable mapped to a corresponding column of the a-CAM array;
• and
• map the multiple paths of the decision tree to rows of the a-CAM array, wherein each path of the multiple paths comprises of a root to leaf path associated with the set of nodes, and wherein each root to leaf path of each path is mapped to a corresponding row of the a-CAM array.