Disk drive biasing two write assist elements using three terminal control circuitry
AssigneeWestern Digital Technologies, Inc.
InventorsJoey M. Poss, John T. Contreras, Ian Robson McFadyen, Yaw Shing Tang
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Abstract
A data storage device is disclosed comprising a storage medium and a head configured to access the storage medium, wherein the head comprises a first write assist element (WA1) comprising a first terminal and a second terminal and a second write assist element (WA2) comprising a first terminal and a second terminal. The second terminal of the WA1 and the second terminal of the WA2 are coupled together to form a common node. A first bias signal is applied to the first terminal of the WA1, a second bias signal is applied to the first terminal of the WA2, and a common mode voltage is applied to the common node.
Claims15
Control circuitry comprising:
- a first current source configured to apply a first bias current to a first terminal of a first write assist element (WA1) of a data storage device;
- a second current source configured to apply a second bias current to a first terminal of a second write assist element (WA2) of the data storage device;
- and
- a voltage generator configured to apply a common mode voltage to a common node of the WA1 and WA2, wherein the voltage generator comprises an amplifier configured to generate the common mode voltage.
A data storage device comprising:
- a storage medium;
- a head configured to access the storage medium, wherein:
- the head comprises a first write assist element (WA1) comprising a first terminal and a second terminal and a second write assist element (WA2) comprising a first terminal and a second terminal;
- and
- the second terminal of the WA1 and the second terminal of the WA2 are coupled together to form a common node;
- and
- control circuitry configured to:
- apply a first bias signal to the first terminal of the WA1;
- apply a second bias signal to the first terminal of the WA2;
- and
- apply a common mode voltage to the common node, wherein the control circuitry comprises an amplifier configured to generate the common mode voltage.
A data storage device comprising:
- a storage medium;
- a head configured to access the storage medium, wherein:
- the head comprises a first write assist element (WA1) comprising a first terminal and a second terminal and a second write assist element (WA2) comprising a first terminal and a second terminal;
- and
- the second terminal of the WA1 and the second terminal of the WA2 are coupled together to form a common node;
- and
- a means for biasing the first terminal of the WA1;
- a means for biasing the first terminal of the WA2;
- and
- a means for voltage biasing the common node of the WA1and the WA2, wherein the means for voltage biasing the common node comprises an amplifier configured to generate a common mode voltage.
A data storage device comprising:
- a storage medium;
- a head configured to access the storage medium, wherein:
- the head comprises a first write assist element (WA1) comprising a first terminal and a second terminal and a second write assist element (WA2) comprising a first terminal and a second terminal;
- and
- the second terminal of the WA1 and the second terminal of the WA2 are coupled together to form a common node;
- and
- a means for biasing the first terminal of the WA1;
- a means for biasing the first terminal of the WA2;
- and
- a means for voltage biasing the common node of the WA1 and the WA2, wherein the means for voltage biasing the common node comprises an amplifier configured to generate a common mode voltage, wherein the common mode voltage is different than a voltage potential of the storage medium.
Dependencies are inferred from the claim text.