Hybrid accumulation method in multiply-accumulate for machine learning

A method of performing a spatial-temporal multiply-accumulate (MAC) operation in an integrated circuit, the method comprising:

• Time multiplexing an apparatus to perform a sequence of a plurality of j steps comprising:
• Starting the time multiplexing of the apparatus at a beginning j step;
• Feeding a plurality of digital weight (PI) signals and a respective plurality of digital activation (QI) signals to a plurality of digital-input to current analog-output multiplier (iMULT) apparatuses to generate a respective plurality of current analog output (PIQI) signals corresponding to a j step of the plurality of j steps;
• Coupling the (PI) signals and the (QI) signals to generate a current summation output (ΣPIQI) signal corresponding to the j step of the plurality of j steps;
• Feeding a digital offset (OFS) signal to a current-mode offset digital-to-analog converter (DACOFS) to generate an offset current (IOFS) signal corresponding to the j step of the plurality of j steps;
• Coupling the (ΣPIQI) signal and IOFS signal to generate a partial current Multiply-Accumulate (iMACP) signal corresponding to the j step of the plurality of j steps;
• Memorizing the (iMACP) signal corresponding to the j step of the plurality of j steps by at least one of current-mode sample-and-hold (iSH) apparatus and current-mode Analog-to-Digital Converter (iADC) apparatus;
• Accumulating the (iMACP) signals corresponding to the j step and j−1 step of the plurality of j steps by at least one of a current-mode accumulator (iACC) apparatus communicating with the (iSH) apparatus and a memory (MEM) apparatus communicating with the (iADC) apparatus;
• Incrementing j by 1 if j<n−1, and returning to the beginning step, otherwise exiting the time multiplexing state machine if j=n−1;
• Generating a final current Multiply-Accumulate (ΣΣPIJQIJ) signal corresponding to j=n−1;
• Wherein 1≤n≤100;
• Wherein 1≤j+1≤100;
• Wherein each of a PQMIN signal≤the (PIQI) signal≤a PQMAX signal;
• Wherein a RI/j signal is half of the sum of the PQMIN signal and the PQMAX signal;
• Wherein the (OFS) signal is programmed to be substantially equal to the RI/j signal;
• and
• Wherein the plurality of (iMULT) apparatuses is configured as at least one of digital-input to current analog-output Binary Neural Network multiplier (iBNN) apparatuses and digital-input to current analog-output multiplying current-mode Digital-to-Analog Converters (iDAC) apparatuses.