US 11,615,225 B2 · Logic simulation of circuit designs using on-the-fly bit reduction for constraint solving

Abstract

A system performs logic simulation of a circuit design specified using a hardware description language such as Verilog. The system performs constraint solving based on an expression specified in the specification of the circuit design. The system identifies required bits for each variable in the expression. The number of required bits is less than the number of bits specified in the variable declaration. The system performs bit-level constraint solving by performing a bit operation on the set of required bits and a simplified processing of the remaining bits of the variable. Since the original circuit design is preserved with the original bit-widths for simulation, those required bits are used on the fly internally during constraint solving. Furthermore, dynamic bit reductions on arithmetic operations are performed on the fly. The system improves computational efficiency by restricting bit operations to fewer bits of variables and operators of the expression.

Claims20

Dependent claims

A method for execution of expressions in logic simulation of a circuit design, the method comprising:

receiving a specification of the circuit design, the specification using a hardware description language;
receiving a request to perform logic simulation of the circuit design;
identifying an expression in the specification of the circuit design, the expression specifying an operation based on a variable, wherein the specification of the circuit design includes a declaration of the variable, wherein evaluation of the operation comprises determining one or more intermediate results;
identifying a set of required bits for the variable used in the expression, wherein a number of required bits in the set of required bits is less than a number of bits specified in the declaration of the variable;
performing, by a processor, bit-level constraint solving using the expression by reducing the number of bits of each of the one or more intermediate results to the set of required bits;
determining a result of logic simulation based on the bit-level constraint solving;
and
sending the result of logic simulation for display.

5 more elements

A non-transitory storage medium storing instructions that when executed by a processor, cause the processor to perform steps comprising:

receiving a specification of a circuit design;
identifying an expression in the specification of the circuit design, the expression specifying an operation based on a variable, wherein the specification of the circuit design includes a declaration of the variable, wherein evaluation of the operation comprises determining one or more intermediate results;
identifying a set of required bits for the variable used in the expression, wherein a number of required bits in the set of required bits is determined based on a limit on the value of the variable, wherein the number of required bits is less than the number of bits specified in the declaration of the variable;
performing bit-level constraint solving using the expression by reducing the number of bits of each of the one or more intermediate results to the set of required bits;
determining a result of logic simulation based on the bit-level constraint solving;
and
sending the result of logic simulation for display.

4 more elements

Dependencies are inferred from the claim text.

Logic simulation of circuit designs using on-the-fly bit reduction for constraint solving

Life of this patent

Logic simulation of circuit designs using on-the-fly bit reduction for constraint solving

Life of this patent

Abstract

Claims20