Multi-capture at-speed scan test based on a slow clock signal
AssigneeSiemens Industry Software Inc.
InventorJean-Francois Cote
Life of this patent
Estimating the term…
Abstract
A circuit comprises a plurality of clock control devices. Each of the clock control devices is configured to generate a scan test clock signal for a particular clock domain in the circuit and comprises circuitry configured to select clock pulses of a fast clock signal as scan capture clock pulses for the particular clock domain based on a particular clock pulse of a slow clock signal and a scan enable signal. The order and spacing between the groups of the scan capture clock pulses for different clock domains correspond to the order and spacing of the clock pulses of the slow clock signal.
Claims20
A circuit, comprising:
- a first clock control device for a first clock domain, the first clock control device receiving signals comprising a first fast clock signal, a test signal, and a slow clock signal, the first clock control device comprising first circuitry configured to select clock pulses of the first fast clock signal as scan capture clock pulses for the first clock domain based on a first clock pulse of the slow clock signal and the test signal;
- and
- a second clock control device for a second clock domain, the second clock control device receiving signals comprising a second fast clock signal, the test signal, and the slow clock signal, the second clock control device comprising second circuitry configured to select clock pulses of the second fast clock signal as scan capture clock pulses for the second clock domain based on a second clock pulse of the slow clock signal and the test signal, wherein the first clock pulse and the second clock pulse are different clock pulses of the slow clock signal.
One or more computer-readable media storing computer-executable instructions for causing a computer to perform a method, the method comprising:
- creating a clock control circuit in a circuit design for testing a chip fabricated according to the circuit design, the clock control circuit comprising:
- a first clock control device for a first clock domain, the first clock control device receiving signals comprising a first fast clock signal, a test signal, and a slow clock signal, the first clock control device comprising first circuitry configured to select clock pulses of the first fast clock signal as scan capture clock pulses for the first clock domain based on a first clock pulse of the slow clock signal and the test signal;
- and
- a second clock control device for a second clock domain, the second clock control device receiving signals comprising a second fast clock signal, the test signal, and the slow clock signal, the second clock control device comprising second circuitry configured to select clock pulses of the second fast clock signal as scan capture clock pulses for the second clock domain based on a second clock pulse of the slow clock signal and the test signal.
Dependencies are inferred from the claim text.