Semiconductor memory device

A semiconductor memory device, comprising:

• a substrate including a first region on which memory cells are provided, a second region on which a control circuit of the memory cells is provided, and a third region separating the first region and the second region;
• a stack of first conductor layers spaced from each other above the first region of the substrate;
• a stack of second conductor layers spaced from each other above an uppermost one of the first conductor layers;
• a semiconductor pillar extending through the stack of first conductor layers and the stack of the second conductor layers;
• a third conductor layer above the second region of the substrate;
• a first insulator layer above the second and third regions of the substrate, the first insulator layer being not provided above the first region of the substrate, the first insulator layer including:
• a first portion that is above the third conductor layer at a height from the substrate greater than a height of the uppermost one of the first conductor layers and extends along a surface direction of the substrate, and
• a second portion that is continuous with the first portion, extends along a thickness direction of the substrate, and is in contact with a surface of the substrate in the third region;
• a second insulator layer provided above the third region between the uppermost one of the first conductor layers and the lowermost one of the second conductor layers;
• a third insulator layer between adjacent two of the first conductor layers;
• and
• a fourth insulator layer between adjacent two of the second conductor layers, wherein
• a thickness of the second insulator layer in the thickness direction is greater than a thickness of the third insulator layer and greater than a thickness of the fourth insulator layer.