Back to results
US 11,610,633 B2Granted
Low-leakage drain-programmed ROM
AssigneeQUALCOMM Incorporated
InventorsXiao Chen, Chen-ju Hsieh, Sung Son, Chulmin Jung
Life of this patent
Estimating the term…
Abstract
A drain programmed read-only memory includes a diffusion region that spans a width of a bitcell and forms a drain of a first transistor and a second transistor. A bit line lead in a metal layer adjacent the diffusion region extends across the width of the bitcell. A first via extends from an upper half of the bit line lead and couples to a drain of the first transistor. Similarly, a second via extends from a lower half of the bit line and couples to a drain of the second transistor.
Claims24
A read-only memory, comprising:
- a semiconductor substrate including a diffusion region configured to form a drain of a first transistor and a drain of a second transistor;
- a metal layer adjacent the diffusion region, the metal layer being configured to include a bit line lead that extends across the diffusion region;
- a first drain via positioned within an upper half of the bit line lead, the first drain via being configured to couple from the upper half of the bit line lead to the drain of the first transistor;
- and
- a second drain via positioned within a lower half of the bit line lead, the second drain via configured to couple from the lower half of the bit line lead to the drain of the second transistor.
2 more elements
A read-only memory, comprising:
- a plurality of bitcells arranged into a row within a bitcell height, each bitcell in the plurality of bitcells including a first transistor and a second transistor;
- a diffusion region configured to extend across the row, the diffusion region being configured for each bitcell in the plurality of bitcells to form a drain of the bitcell's first transistor and to form a drain of the bitcell's second transistor;
- and
- a metal layer adjacent the diffusion region, the metal layer being configured to include a bit line lead that extends across the row;
- wherein each bitcell in a first subset of the plurality of bitcells is configured to include a first drain via positioned on and coupled from a lower half of the bit line lead to the drain of the bitcell's first transistor and to include a second drain via positioned on and coupled from an upper half of the bit line lead to the drain of the bitcell's second transistor and, and wherein each bitcell in a second subset of the plurality of bitcells is configured to electrically isolate both the drain of the bitcell's first transistor and the drain of the bitcell's second transistor from the bit line lead.
2 more elements
A method of operating a read-only memory, comprising;
- asserting a voltage of a first word line coupled to a gate of a first transistor arranged in a row within a bitcell height with a second transistor to cause the first transistor to conduct charge from a first drain via positioned on an upper half of a bit line lead to ground through a first ground via positioned on a first ground lead having a central longitudinal axis substantially aligned with an upper boundary of the bitcell height;
- and
- asserting a voltage of a second word line coupled to a gate of the second transistor to cause the second transistor to conduct charge from a second drain via positioned on a lower half of the bit line lead to ground through a second ground via positioned on a second ground lead having a central longitudinal axis substantially aligned with a lower boundary of the bitcell height.
A read-only memory, comprising:
- a diffusion region configured to extend from a first side of a bitcell to a second side of the bitcell;
- a first dummy gate aligned with the first side of the bitcell;
- a second dummy gate aligned with the second side of the bitcell;
- a gate of a first transistor adjacent the first dummy gate and configured to extend from a lower boundary of the bitcell and across the diffusion region to an upper boundary of the bitcell;
- a gate of a second transistor arranged between the gate of the first transistor and the second dummy gate, wherein the diffusion region is further configured to form a drain of the first transistor positioned between the first dummy gate and the gate of the first transistor, a shared source of the first transistor and the second transistor positioned between the gate of the first transistor and the gate of the second transistor, and a drain of the second transistor positioned between the gate of the second transistor and the second dummy gate;
- a metal layer adjacent the diffusion region, the metal layer being configured to form a bit line lead having a height, the metal layer being further configured to form a first ground lead having a central longitudinal axis substantially aligned with the upper boundary of the height of the bitcell;
- and
- a first via positioned on a first half of the height of the bit line lead and coupled to the drain of the first transistor, wherein a drain of the second transistor is isolated from bit line lead.
5 more elements
Dependencies are inferred from the claim text.