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AssigneeSamsung Electronics Co., Ltd.
InventorsJiwoong Kim, Dongjoo Kim, Jaekuk Park, Yujin Oh, Moonki Jang, Jieun Jeong
Estimating the term…
A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.
A system-on-chip (SoC), comprising:
A system-on-chip (SoC), comprising:
An automotive system-on-chip (SoC), comprising:
Dependencies are inferred from the claim text.