Ultra-wideband ground penetrating radar control system

An ultra-wideband ground penetrating radar control system, comprising:

• a synchronous clock generating circuit,
• a GPS positioning module,
• a measuring wheel encoder module,
• a digitally controlled delay circuit for equivalent sampling,
• an analog-to-digital conversion circuit, and
• a main controller, wherein
• the synchronous clock generating circuit, the GPS positioning module, the measuring wheel encoder module, the digitally controlled delay circuit and the analog-to-digital conversion circuit are all connected to the main controller;
• the synchronous clock generating circuit is connected to an ultra-wideband transmitter and receiver;
• the digitally controlled delay circuit and the analog-to-digital conversion circuit are connected to an external sampling gate for equivalent sampling;
• the main controller is connected to an external server,
• the synchronous clock generating circuit comprises a crystal oscillator, a chip, a first resistor, a fifth resistor, a sixth resistor, a 50th resistor, a first capacitor, a second capacitor, a third capacitor, a fifth capacitor, a 50th capacitor, a first inductor and a second inductor, wherein
• a first pin of the crystal oscillator is connected to the positive electrode of a power supply via the first inductor;
• one terminal of the second capacitor is connected to the first pin of the crystal oscillator, the other terminal of the second capacitor is grounded;
• one terminal of the first capacitor is connected to the positive electrode of the power supply, the other terminal of the first capacitor is connected to the ground terminal of the second capacitor;
• one terminal of the fifth resistor is connected to a second pin of the crystal oscillator, the other terminal of the fifth resistor is connected to a first pin and a second pin of the chip;
• third, fourth, fifth, ninth, 10th, 11th and 13th pins of the chip are connected together;
• a 14th pin of the chip, the positive electrode of the power supply and one terminal of the 50th capacitor are connected, and the other terminal of the 50th capacitor is grounded;
• a sixth pin of the chip, the sixth resistor, the second inductor, the first resistor and an output interface are connected in sequence, the output interface is grounded, the output interface is connected to the ultra-wideband transmitter;
• the sixth resistor is connected to the connecting terminal of the second inductor and one terminal of the fifth capacitor, the other terminal of the fifth capacitor is grounded;
• the first resistor is connected to the connecting terminal of the second inductor and one terminal of the third capacitor, the other terminal of the third capacitor is connected to a ground terminal of the fifth capacitor;
• an 11th pin of the chip is connected to one terminal of the 50th capacitor, the other terminal of the 50th capacitor is connected to the main controller,
• the GPS positioning module comprises a GPS chip, a low noise amplifier chip, a surface acoustic wave filter chip, a second resistor, a third resistor, a fourth resistor, a sixth capacitor, a seventh capacitor, a third inductor, a fourth inductor, a diode, a light-emitting diode (LED), a battery and an antenna interface;
• wherein
• an 11th pin of the GPS chip is connected to a fourth pin of the surface acoustic wave filter chip;
• one terminal of the fourth resistor is connected to eighth and ninth pins of the GPS chip, and the other terminal of the fourth resistor is connected to the antenna interface via the third inductor, the antenna interface is grounded;
• a 22th pin of the GPS chip, the second resistor, the diode and the positive electrode of a power supply are connected in sequence;
• and the positive electrode of the battery is connected to the 22th pin of the GPS chip, the negative electrode of the battery is grounded, and a 24th pin of the GPS chip is connected to the negative electrode of the battery;
• a third pin of the GPS chip, the third resistor, and the LED are connected in sequence, and the negative electrode of the LED is grounded;
• 18th, 19th, 20th and 21th pins of the GPS chip are SPI bus interfaces, a first pin and a second pin of the GPS chip and the SPI bus interfaces are all connected to the main controller;
• a first pin of the surface acoustic wave filter chip is connected to a fourth pin of the low noise amplifier, a third pin of the low noise amplifier, the fourth inductor, the sixth capacitor and the antenna interface are connected in sequence;
• a fifth pin and a sixth pin of the low noise amplifier are connected to the positive electrode of the power supply, and one terminal of the seventh capacitor is connected to the positive electrode of the power supply, the other terminal of the seventh capacitor is grounded,
• the digitally controlled delay circuit comprises a delay chip, a seventh resistor, an eighth resistor, a ninth resistor, a 10th resistor, an 11th resistor, a 12th resistor and an eighth capacitor;
• first, second, third, fourth, fifth, 23th, 26th, 27th, 29th, 30th, 31th and 32th pins of the delay chip are connected to the main controller;
• 20th and 21th pins of the delay chip are differential output ports, wherein the 20th pin of the delay chip, the seventh resistor, the 10th resistor, the 11th resistor and a ground port are connected in sequence;
• one terminal of the 12th resistor is connected to the 10th resistor, the other terminal of the 10th resistor is connected to the ground terminal of the 11th resistor;
• one terminal of the ninth resistor is connected to the positive electrode of a power supply, the other terminal of the ninth resistor is connected to a second terminal of the 10th resistor away from the 11th resistor;
• one terminal of the eighth capacitor is connected to the ground terminal of the 11th resistor, the other terminal of the 11th resistor is connected to the connecting terminals of the ninth resistor and the 10th resistor;
• the 21th pin of the delay chip is connected to the external sampling gate for equivalent sampling via a second output interface;
• one terminal of the eighth resistor is connected to the 21th pin of the delay chip, the other terminal of the eighth resistor is connected to the connecting terminals of the ninth resistor and the 10th resistor,
• the analog-to-digital conversion circuit comprises an ADC chip, a 13th resistor array, a 14th resistor array, a 15th resistor array, a ninth capacitor, a 10th capacitor, an 11th capacitor, a 12th capacitor, and a 49th capacitor, wherein
• 23th, 24th and 25th pins of the ADC chip are connected to the external sampling gate for equivalent sampling, 19th, 20th, 21th and 22th pins of the ADC chip are connected to the ninth capacitor, the 10th capacitor, the 11th capacitor and the 12th capacitor, respectively, and then the ninth capacitor, the 10th capacitor, the 11th capacitor and the 12th capacitor are grounded;
• a 15th pin of the ADC chip is connected to one terminal of the 49th capacitor and a power supply, and the other terminal of the 49th capacitor is grounded;
• second, third, fourth and fifth pins of the ADC chip are connected to one terminal of the 13th resistor array, sixth, seventh, eighth and ninth pins are connected to one terminal of the 14th resistor array, 10th, 11th and 14th pins are connected to one terminal of the 15th resistor array, and the other terminals of the 13th resistor array, the 14th resistor array and the 15th resistor array are connected to the main controller;
• a first pin and a 13th pin of the ADC chip are grounded, the 13th pin of the ADC chip is connected to the power supply,
• the main controller comprises a XC7Z020CLG484 chip, a DDR3 memory, a network card chip and a SD memory card,
• the XC7Z020CLG484 chip comprising a FPGA and an ARM processor, wherein
• the FPGA comprises a GPS control module, a measuring wheel encoder signal receiving module, a receiver and transmitter synchronization control module, a global control module, and two Intellectual Property IP cores of Advanced Extensible Interface AXI DataMover and AXI Interconnect;
• the two IP cores AXI DataMover and AXI Interconnect are used for data communication between the GPS control module, the global control module and the receiver and transmitter synchronization control module and the ARM processor;
• the GPS control module is externally connected to the GPS positioning module, and internally connected via AXI4-Lite bus to the AXI Interconnect IP core, the AXI Interconnect IP core is further connected to the global control module and the ARM processor;
• the measuring wheel encoder signal receiving module is externally connected to the measuring wheel encoder, and internally connected to the global control module and the receiver and transmitter synchronization control module;
• the receiver and transmitter synchronization control module is externally connected to the synchronous clock generating circuit, the digitally controlled delay circuit and the analog-to-digital conversion circuit, and internally connected to the AXI DataMover IP core via AXI4-Stream bus;
• the AXI DataMover IP core is further connected to the global control module via AXI4-Stream bus and also connected to a high-performance data bus of the ARM processor via AXI4 bus;
• the ARM processor is connected to the external SD card, the network card chip and the DDR3 memory via an on-chip controller,
• a control system software comprises a Linux operating system, a radar hardware driver and a radar control program, wherein the Linux operating system is stored in the external SD card, and the ARM processor transfers the Linux operating system on the external SD card to the DDR3 memory and runs the Linux operating system, the radar control program runs on the Linux operating system, and controls a hardware circuit of the ultra-wideband ground penetrating radar control system and obtains radar data by calling the radar hardware driver, and also, the radar control program sends the radar data obtained by the hardware circuit to the external server by calling a network card driver of the Linux operating system.