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US 11,606,524 B2Granted
CTIA CMOS image sensor pixel with zero-biased multiplexer
AssigneeSony Group Corporation
InventorEric Bohannon
Life of this patent
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Abstract
An image sensor and pixel circuit therefor includes a plurality of photoelectric conversion devices, a zero-biased multiplexer connected to the plurality of photoelectric conversion devices, an amplifier including a first input terminal connected to the zero-biased multiplexer, and an output terminal, a capacitor disposed between the first input terminal and the output terminal, and a reset switch disposed between the first input terminal and the output terminal in parallel with the capacitor, the reset switch including a body terminal connected to a common reference voltage.
Claims16
A pixel circuit, comprising:
- a plurality of photoelectric conversion devices;
- a zero-biased multiplexer connected to the plurality of photoelectric conversion devices;
- an amplifier including a first input terminal connected to the zero-biased multiplexer, and an output terminal;
- a capacitor disposed between the first input terminal and the output terminal;
- and
- a reset switch disposed between the first input terminal and the output terminal in parallel with the capacitor, the reset switch including a body terminal connected to a common reference voltage,
- wherein the zero-biased multiplexer includes a pair of switches connected to each of the plurality of photoelectric conversion devices,
- wherein a first switch of the pair of switches includes a first electrode connected to the first input terminal and a second electrode connected to a first electrode of the each of the plurality of photoelectric conversion devices, and
- wherein a second electrode of the each of the plurality of photoelectric conversion devices is connected to a cathode voltage.
6 more elements
A pixel circuit, comprising:
- a zero-biased multiplexer;
- an amplifier including a first input terminal connected to the zero-biased multiplexer, and an output terminal;
- a capacitor disposed between the first input terminal and the output terminal;
- a reset switch network disposed between the first input terminal and the output terminal in parallel with the capacitor, the reset switch network including a first reset transistor with a first body terminal connected to a common reference voltage, a second reset transistor, and a third reset transistor;
- and
- a plurality of pixels arranged in an array, a first pixel of the plurality of pixels including a first photoelectric conversion device that is connected to the zero-biased multiplexer, and a second pixel of the plurality of pixels including a second photoelectric conversion device that is connected to the zero-biased multiplexer,
- wherein the zero-biased multiplexer includes a first pair of switches connected to the first photoelectric conversion device and a second pair of switches connected to the second photoelectric conversion device,
- wherein a first switch of the first pair of switches includes a first electrode connected to the first input terminal and a second electrode connected to a first electrode of the first photoelectric conversion device, wherein a first switch of the second pair of switches includes a first electrode connected to the first input terminal and a second electrode connected to a first electrode of the second photoelectric conversion device, and
- wherein respective second electrodes of the first photoelectric conversion device and the second photoelectric conversion device are connected to a cathode voltage.
6 more elements
A pixel circuit, comprising:
- a zero-biased multiplexer;
- an amplifier including a first input terminal connected to the zero-biased multiplexer, and an output terminal;
- a capacitor disposed between the first input terminal and the output terminal;
- a reset switch network disposed between the first input terminal and the output terminal in parallel with the capacitor, the reset switch network including a first reset transistor with a first body terminal connected to a common reference voltage, a second reset transistor, and a third reset transistor;
- and
- a plurality of pixels arranged in an array, a first pixel of the plurality of pixels including a first photoelectric conversion device that is connected to the zero-biased multiplexer, and a second pixel of the plurality of pixels including a second photoelectric conversion device that is connected to the zero-biased multiplexer, wherein
- the first reset transistor and the third reset transistor are connected in series between the first input terminal and the output terminal, and
- one of a source terminal or a drain terminal of the second reset transistor is connected to a node between the first reset transistor and the third reset transistor.
5 more elements
A pixel circuit, comprising:
- a zero-biased multiplexer;
- an amplifier including a first input terminal connected to the zero-biased multiplexer, and an output terminal;
- a capacitor disposed between the first input terminal and the output terminal;
- a reset switch network disposed between the first input terminal and the output terminal in parallel with the capacitor, the reset switch network including a first reset transistor with a first body terminal connected to a common reference voltage, a second reset transistor, and a third reset transistor;
- and
- a plurality of pixels arranged in an array, a first pixel of the plurality of pixels including a first photoelectric conversion device that is connected to the zero-biased multiplexer, and a second pixel of the plurality of pixels including a second photoelectric conversion device that is connected to the zero-biased multiplexer, wherein
- during a reset state of the pixel circuit, the first reset transistor is in a closed state, the second reset transistor is in an open state, and the third reset transistor is in the closed state, and
- during an integration state of the first photoelectric conversion device, the first reset transistor is in the open state, the second reset transistor is in the closed state, and the third reset transistor is in the open state.
5 more elements
Dependencies are inferred from the claim text.