Image sensor having reduced parasitic capacitance

An image sensor, comprising:

• a pixel array including a plurality of pixels connected to row lines extending in a first direction and column lines extending in a second direction intersecting the first direction;
• and
• a sampling circuit including a plurality of comparators and connected to the column lines, wherein the plurality of comparators include circuit elements disposed on a substrate and a plurality of metal-oxide semiconductor (MOS) capacitors configured to determine a bandwidth of an output signal,
• wherein the plurality of comparators includes odd comparators connected to odd-numbered column lines and even comparators connected to even-numbered column lines,
• wherein the plurality of MOS capacitors includes odd MOS capacitors corresponding to the odd comparators and even MOS capacitors corresponding to the even comparators,
• wherein the odd MOS capacitors are disposed in a first position in the second direction, and the even MOS capacitors are disposed in a second position in the second direction,
• wherein the second position is different from the first position, and
• wherein the odd numbered column lines are empty at the second position in the second direction, and the even-numbered column lines are empty at the first position in the second direction.

An image sensor, comprising:

• a pixel array including a plurality of pixels connected to a plurality of row lines extending in a first direction and a plurality of column lines;
• and
• a plurality of comparators connected to the column lines, and disposed in a plurality of unit regions arranged in the first direction,
• wherein the plurality of comparators includes a first comparator adjacent to a second comparator,
• wherein a first transistor of the first comparator is arranged consecutively with a second transistor of the first comparator,
• wherein a first transistor of the second comparator is disposed consecutively with a second transistor of the second comparator, and
• wherein a gap between the first transistor of the first comparator and the second transistor of the first comparator is smaller than a gap between the first transistor of the second comparator and the second transistor of the second comparator.