Clock synchronization
AssigneeAcacia Communications, Inc.
InventorsJames Duda, Jon Stahl, Kevin Hinchey
Life of this patent
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Abstract
A method, system, and apparatus for determining delay between clocks, in response to a trigger event, buffering DSP symbol information in a symbol capture buffer; wherein the amount of DSP symbol information buffered corresponds to the amount of symbols captured during a buffer storage interval; and extracting a synchronization packet from the symbol capture buffer.
Claims20
A method for determining delay between clocks of a first coherent transceiver and a second coherent transceiver in a coherent optical system, the method comprising:
- in response to a trigger event, buffering digital signal processor (DSP) symbol information in a symbol capture buffer of the first coherent transceiver;
- wherein the amount of DSP symbol information buffered corresponds to the amount of symbols captured during a buffer storage interval;
- extracting a synchronization packet from the symbol capture buffer;
- wherein the symbol capture buffer is located within a coherent optical DSP of the first coherent transceiver;
- and
- calculating a total Egress TX delay by summing an Egress system-side delay, a Fixed Delay D1, Egress line-side delay, and Fixed Delay D2.
A system for determining delay between clocks of a first coherent transceiver and a second coherent transceiver in a coherent optical system, the system comprising:
- a symbol capture buffer;
- wherein the symbol capture buffer is enabled to storage symbols received during a buffer storage interval;
- wherein the symbol capture buffer is located within a digital signal processor (DSP) of a first coherent transceiver;
- and
- logic;
- wherein the logic is enabled to extract a synchronization packet from the symbol capture buffer and calculate a total Egress TX delay by summing an Egress system-side delay, a Fixed Delay D1, Egress line-side delay, and Fixed Delay D2.
A coherent optical system apparatus comprising:
- a symbol capture buffer;
- wherein the symbol capture buffer is enabled to storage symbols received during a buffer storage interval;
- wherein the symbol capture buffer is located within a digital signal processor (DSP) of a first coherent transceiver;
- and
- logic;
- wherein the logic is enabled to extract a synchronization packet from the symbol capture buffer of the DSP and calculate a total Egress TX delay by summing an Egress system-side delay, a Fixed Delay D1, Egress line-side delay, and Fixed Delay D2.
Dependencies are inferred from the claim text.