Transceiver performing internal loopback test and operation method thereof

An interface circuit implemented on one chip, the interface circuit comprising:

• transmission pads configured to output serial transmission data to an outside of the one chip;
• reception pads configured to receive serial reception data from the outside of the one chip;
• and
• a transceiver configured to:
• generate the serial transmission data or to process the serial reception data in a normal mode, and
• form a loop in an interior of the transceiver, and to generate test result data based on the serial transmission data in a test mode,
• wherein the transceiver includes:
• a logic circuit configured to generate parallel transmission data;
• a serializer configured to convert the parallel transmission data into the serial transmission data;
• a driver configured to output the serial transmission data through the transmission pads;
• an analog circuit configured to receive the serial reception data through the reception pads;
• a deserializer configured to convert the serial reception data into parallel reception data;
• and
• a test circuit electrically connected to the analog circuit in the test mode, and configured to output serial post data corresponding to the serial transmission data to the analog circuit, the test circuit including:
• a resistor ladder including a plurality of variable resistors connected in series between a first voltage node and a second voltage node;
• and
• a plurality of multiplexers connected to different nodes between the plurality of variable resistors.

An operation method of a transceiver that includes an analog circuit and a test circuit, the method comprising:

• generating parallel transmission data in response to a test mode signal;
• converting the parallel transmission data into serial transmission data;
• generating serial post data corresponding to the serial transmission data;
• converting the serial post data into parallel post data;
• and
• comparing the parallel post data and the parallel transmission data to generate test result data,
• wherein the test circuit includes:
• a resistor ladder including a plurality of variable resistors connected in series between a first voltage node and a second voltage node;
• and
• a first multiplexer and a second multiplexer connected to different nodes between the plurality of variable resistors.