Operating clock generator and reference clock gating circuit

An operating clock generator, comprising:

• a reference clock gating circuit configured to perform a detection operation and thereby output a reference clock according to an external clock, wherein the external clock is originated from an external clock source, the operating clock generator and the external clock source are separate and not included in one integrated circuit, and the reference clock gating circuit includes:
• a detection circuit including:
• a first counter configured to count according to triggers of the external clock and thereby generate a first clock number;
• a second counter configured to count according to triggers of a slow clock and thereby generate a second clock number, wherein a frequency of the slow clock is lower than a frequency of the external clock and the slow clock is originated from a crystal oscillator;
• and
• a decision circuit configured to determine whether a ratio of the first clock number to the second clock number satisfies a predetermined condition after the second clock number reaches K times a predetermined number, and accordingly generate a gating signal, wherein the K is a positive integer;
• and
• a gating component configured to receive the external clock and output the external clock as the reference clock in a circumstance that the detection operation is performed and the gating signal indicates that the ratio satisfies the predetermined condition, and the gating component configured to reject the external clock in a circumstance that the detection operation is performed and the gating signal indicates that the ratio does not satisfy the predetermined condition;
• and
• an operating clock generating circuit coupled to the gating component and configured to generate an operating clock according to the reference clock.