Adjustable phase shifter
AssigneeInternational Business Machines Corporation
InventorsYang You, Chad Andrew Marquart, Glen A. Wiedemeier, Tyler Bohlke, Daniel M. Dreps
Life of this patent
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Abstract
A method includes determining a phase error for a first clock signal and a second clock signal and determining an offset based on the phase error for the first clock signal and the second clock signal. The method also includes adding the offset to a phase of the first clock signal to produce a first adjusted clock signal and subtracting the offset from a phase of the second clock signal to produce a second adjusted clock signal. A phase error for the first adjusted clock signal and the second adjusted clock signal is smaller than the phase error for the first clock signal and the second clock signal.
Claims19
A method comprising:
- determining a phase error for a first clock signal and a second clock signal;
- determining an offset based on the phase error for the first clock signal and the second clock signal;
- adjusting a control bit to connect a capacitor to the first clock signal to add the offset to a phase of the first clock signal to produce a first adjusted clock signal;
- and
- subtracting the offset from a phase of the second clock signal to produce a second adjusted clock signal, wherein a phase error for the first adjusted clock signal and the second adjusted clock signal is smaller than the phase error for the first clock signal and the second clock signal.
A phase adjustor comprising:
- a first adjustor;
- a second adjustor;
- and
- a control line connected to the first adjustor and the second adjustor, wherein the first adjustor is configured to produce a first adjusted clock signal by:
- adding an offset to a phase of a first clock signal when a control signal on the control line is high;
- and
- subtracting the offset from the phase of the first clock signal when the control signal is low;
- and
- wherein the second adjustor is configured to produce a second adjusted clock signal by:
- subtracting the offset from a phase of a second clock signal when the control signal is high;
- and
- adding the offset to the phase of the second clock signal when the control signal is low, wherein the offset is determined based on a phase error for the first clock signal and the second clock signal.
A method comprising:
- determining an offset based on a phase error for a first clock signal and a second clock signal;
- toggling a first switch such that the offset is added to a phase of the first clock signal to produce a first adjusted clock signal;
- and
- toggling a second switch such that the offset is subtracted from a phase of the second clock signal to produce a second adjusted clock signal, wherein a phase error for the first adjusted clock signal and the second adjusted clock signal is smaller than the phase error for the first clock signal and the second clock signal.
Dependencies are inferred from the claim text.