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US 11,605,636 B2Granted
Multi-layer random access memory and methods of manufacture
AssigneeTC Lab, Inc.
InventorHarry Luan
Life of this patent
Estimating the term…
Abstract
A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.
Claims8
A semiconductor fabrication process comprising:
- depositing alternating layers of insulating material and first material on a semiconductor substrate;
- etching trenches through the alternating layers;
- removing the first material by laterally etching it from between the layers of insulating material to form cavities between the layers of insulating material;
- beginning a process of forming epitaxial silicon in the cavities;
- introducing conductivity type impurities into the process of forming epitaxial silicon as the process continues to thereby form semiconductor devices in the cavities with the epitaxial silicon;
- and
- providing electrical connections to the semiconductor devices.
4 more elements
Dependencies are inferred from the claim text.